[llvm] [TTI][RISCV] Unconditionally break critical edges to sink ADDI (PR #108889)

[Philip Reames via llvm-commits]

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@@ -78,6 +78,10 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
 
   bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
 
+  bool shouldBreakCriticalEdgeToSink(MachineInstr &MI) const override {
+    return MI.getOpcode() == RISCV::ADDI;
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preames wrote:

It could be.  I left it unconstrained thinking we should probably always be sinking the addi, but if you want, I can add the restriction and it should change any of the diffs.

https://github.com/llvm/llvm-project/pull/108889