[llvm] [AMDGPU][MC] Implement fft and rotate modes for ds_swizzle_b32 (PR #108064)
Jun Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 16 15:11:24 PDT 2024
https://github.com/jwanggit86 updated https://github.com/llvm/llvm-project/pull/108064
>From acc96ee5ab23c0776fc1176228ec44052ff2e2d9 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Tue, 10 Sep 2024 11:02:14 -0700
Subject: [PATCH 1/6] [AMDGPU][MC] Implement fft and rotate modes for
ds_swizzle_b32
In addition to the basic mode, the ds_swizzle_b32 is supposed to
support two specific modes: fft and rotate. This patch implements
those two modes.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 56 +++++++++++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 7 ++
llvm/lib/Target/AMDGPU/SIDefines.h | 26 +++++-
.../Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 9 +-
llvm/test/MC/AMDGPU/ds_swizzle.s | 93 +++++++++++++++++++
5 files changed, 183 insertions(+), 8 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/ds_swizzle.s
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 1a10206eea2374..b1516df77dce7d 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1843,6 +1843,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool parseSwizzleBroadcast(int64_t &Imm);
bool parseSwizzleSwap(int64_t &Imm);
bool parseSwizzleReverse(int64_t &Imm);
+ bool parseSwizzleFFT(int64_t &Imm);
+ bool parseSwizzleRotate(int64_t &Imm);
ParseStatus parseGPRIdxMode(OperandVector &Operands);
int64_t parseGPRIdxMacro();
@@ -8141,6 +8143,56 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
return true;
}
+bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
+ using namespace llvm::AMDGPU::Swizzle;
+
+ if (!skipToken(AsmToken::Comma, "expected a comma"))
+ return false;
+
+ SMLoc Loc = getLoc();
+
+ int64_t Type;
+
+ if (!parseExpr(Type))
+ return false;
+
+ if (Type != FFT_NO_SWIZZLE && Type != FFT_SWIZZLE_00 &&
+ Type != FFT_SWIZZLE_10) {
+ const std::string ErrMsg = "invalid FFT swizzle type: must be " +
+ std::to_string(FFT_SWIZZLE_00) + ", " +
+ std::to_string(FFT_SWIZZLE_10) + ", or " +
+ std::to_string(FFT_NO_SWIZZLE);
+ Error(Loc, ErrMsg);
+ return false;
+ }
+
+ Imm = FFT_MODE_ENC | Type;
+ return true;
+}
+
+bool AMDGPUAsmParser::parseSwizzleRotate(int64_t &Imm) {
+ using namespace llvm::AMDGPU::Swizzle;
+
+ SMLoc Loc;
+ int64_t Direction;
+
+ if (!parseSwizzleOperand(Direction, 0, 1,
+ "direction must be 0 (left) or 1 (right)", Loc))
+ return false;
+
+ int64_t RotateSize;
+ const std::string ErrorMsg =
+ "number of threads to rotate must be in the interval [0," +
+ std::to_string(ROTATE_MAX_SIZE) + "]";
+
+ if (!parseSwizzleOperand(RotateSize, 0, ROTATE_MAX_SIZE, ErrorMsg, Loc))
+ return false;
+
+ Imm = ROTATE_MODE_ENC | (Direction << ROTATE_DIR_SHIFT) |
+ (RotateSize << ROTATE_SIZE_SHIFT);
+ return true;
+}
+
bool
AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
@@ -8175,6 +8227,10 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
Ok = parseSwizzleSwap(Imm);
} else if (trySkipId(IdSymbolic[ID_REVERSE])) {
Ok = parseSwizzleReverse(Imm);
+ } else if (trySkipId(IdSymbolic[ID_FFT])) {
+ Ok = parseSwizzleFFT(Imm);
+ } else if (trySkipId(IdSymbolic[ID_ROTATE])) {
+ Ok = parseSwizzleRotate(Imm);
} else {
Error(ModeLoc, "expected a swizzle mode");
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 94bf5e4b95270b..a9f660b7e9b86f 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1556,6 +1556,13 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
O << ")";
}
}
+ } else if ((Imm & FFT_ROTATE_MODE_MASK) == FFT_MODE_ENC) {
+ O << "swizzle(" << IdSymbolic[ID_FFT] << ","
+ << (Imm & FFT_SWIZZLE_TYPE_MASK) << ")";
+ } else if ((Imm & FFT_ROTATE_MODE_MASK) == ROTATE_MODE_ENC) {
+ O << "swizzle(" << IdSymbolic[ID_ROTATE] << ","
+ << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ","
+ << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ")";
} else {
printU16ImmDecOperand(MI, OpNo, O);
}
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index fb3d83ca30d198..40cd022cc33aa6 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -841,7 +841,9 @@ enum Id : unsigned { // id of symbolic names
ID_BITMASK_PERM,
ID_SWAP,
ID_REVERSE,
- ID_BROADCAST
+ ID_BROADCAST,
+ ID_FFT,
+ ID_ROTATE
};
enum EncBits : unsigned {
@@ -854,6 +856,11 @@ enum EncBits : unsigned {
BITMASK_PERM_ENC = 0x0000,
BITMASK_PERM_ENC_MASK = 0x8000,
+ FFT_MODE_ENC = 0xE000,
+
+ ROTATE_MODE_ENC = 0xC000,
+ FFT_ROTATE_MODE_MASK = 0xF000,
+
// QUAD_PERM encodings
LANE_MASK = 0x3,
@@ -869,7 +876,22 @@ enum EncBits : unsigned {
BITMASK_AND_SHIFT = 0,
BITMASK_OR_SHIFT = 5,
- BITMASK_XOR_SHIFT = 10
+ BITMASK_XOR_SHIFT = 10,
+
+ // FFT encodings
+
+ FFT_NO_SWIZZLE = 0x1F,
+ FFT_SWIZZLE_00 = 0x0,
+ FFT_SWIZZLE_10 = 0x10,
+
+ FFT_SWIZZLE_TYPE_MASK = 0x1F,
+
+ // ROTATE encodings
+ ROTATE_MAX_SIZE = 0x1F,
+ ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
+ ROTATE_DIR_MASK = 0x1,
+ ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
+ ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
};
} // namespace Swizzle
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
index 5f7549c2921eda..702a0d6118bbae 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
@@ -646,12 +646,9 @@ unsigned const DfmtNfmt2UFmtGFX11[] = {
namespace Swizzle {
// This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
-const char* const IdSymbolic[] = {
- "QUAD_PERM",
- "BITMASK_PERM",
- "SWAP",
- "REVERSE",
- "BROADCAST",
+const char *const IdSymbolic[] = {
+ "QUAD_PERM", "BITMASK_PERM", "SWAP", "REVERSE",
+ "BROADCAST", "FFT", "ROTATE",
};
} // namespace Swizzle
diff --git a/llvm/test/MC/AMDGPU/ds_swizzle.s b/llvm/test/MC/AMDGPU/ds_swizzle.s
new file mode 100644
index 00000000000000..7d9f5097edbd54
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/ds_swizzle.s
@@ -0,0 +1,93 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
+
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
+
+//==============================================================================
+// FFT mode
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0)
+// CHECK: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16)
+// CHECK: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31)
+// CHECK: [0x1f,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x1f,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,2)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid FFT swizzle type: must be 0, 16, or 31
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,32)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid FFT swizzle type: must be 0, 16, or 31
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16,31)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
+
+
+//==============================================================================
+// ROTATE mode
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0)
+// CHECK: [0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0)
+// CHECK: [0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1)
+// CHECK: [0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1)
+// CHECK: [0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31)
+// CHECK: [0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31)
+// CHECK: [0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,2,31)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,-1,31)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,32)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,-2)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+
+ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1,2)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
+
+
+
+
>From 3d9b5f45d440b23223db6d69d6b4401f20711683 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Wed, 11 Sep 2024 12:31:31 -0700
Subject: [PATCH 2/6] Fix a mistake in previous commit: for FFT mode, the
swizzle value is in [0,31].
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 36 +++++---------
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIDefines.h | 47 +++++++++----------
llvm/test/MC/AMDGPU/ds_swizzle.s | 12 +++--
4 files changed, 44 insertions(+), 55 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index b1516df77dce7d..367d4f68155540 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -8146,27 +8146,15 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
using namespace llvm::AMDGPU::Swizzle;
- if (!skipToken(AsmToken::Comma, "expected a comma"))
- return false;
-
- SMLoc Loc = getLoc();
-
- int64_t Type;
-
- if (!parseExpr(Type))
- return false;
-
- if (Type != FFT_NO_SWIZZLE && Type != FFT_SWIZZLE_00 &&
- Type != FFT_SWIZZLE_10) {
- const std::string ErrMsg = "invalid FFT swizzle type: must be " +
- std::to_string(FFT_SWIZZLE_00) + ", " +
- std::to_string(FFT_SWIZZLE_10) + ", or " +
- std::to_string(FFT_NO_SWIZZLE);
- Error(Loc, ErrMsg);
+ int64_t Swizzle;
+ SMLoc Loc;
+ if (!parseSwizzleOperand(Swizzle, 0, FFT_SWIZZLE_MAX,
+ "FFT swizzle must be in the interval [0," +
+ Twine(FFT_SWIZZLE_MAX).str() + Twine(']').str(),
+ Loc))
return false;
- }
- Imm = FFT_MODE_ENC | Type;
+ Imm = FFT_MODE_ENC | Swizzle;
return true;
}
@@ -8181,11 +8169,11 @@ bool AMDGPUAsmParser::parseSwizzleRotate(int64_t &Imm) {
return false;
int64_t RotateSize;
- const std::string ErrorMsg =
- "number of threads to rotate must be in the interval [0," +
- std::to_string(ROTATE_MAX_SIZE) + "]";
-
- if (!parseSwizzleOperand(RotateSize, 0, ROTATE_MAX_SIZE, ErrorMsg, Loc))
+ if (!parseSwizzleOperand(
+ RotateSize, 0, ROTATE_MAX_SIZE,
+ "number of threads to rotate must be in the interval [0," +
+ Twine(ROTATE_MAX_SIZE).str() + Twine(']').str(),
+ Loc))
return false;
Imm = ROTATE_MODE_ENC | (Direction << ROTATE_DIR_SHIFT) |
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index a9f660b7e9b86f..ee09d0aeb290ea 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1557,8 +1557,8 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
}
}
} else if ((Imm & FFT_ROTATE_MODE_MASK) == FFT_MODE_ENC) {
- O << "swizzle(" << IdSymbolic[ID_FFT] << ","
- << (Imm & FFT_SWIZZLE_TYPE_MASK) << ")";
+ O << "swizzle(" << IdSymbolic[ID_FFT] << "," << (Imm & FFT_SWIZZLE_MASK)
+ << ")";
} else if ((Imm & FFT_ROTATE_MODE_MASK) == ROTATE_MODE_ENC) {
O << "swizzle(" << IdSymbolic[ID_ROTATE] << ","
<< ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ","
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 40cd022cc33aa6..30e526da6c250a 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -850,47 +850,44 @@ enum EncBits : unsigned {
// swizzle mode encodings
- QUAD_PERM_ENC = 0x8000,
- QUAD_PERM_ENC_MASK = 0xFF00,
+ QUAD_PERM_ENC = 0x8000,
+ QUAD_PERM_ENC_MASK = 0xFF00,
- BITMASK_PERM_ENC = 0x0000,
+ BITMASK_PERM_ENC = 0x0000,
BITMASK_PERM_ENC_MASK = 0x8000,
- FFT_MODE_ENC = 0xE000,
+ FFT_MODE_ENC = 0xE000,
- ROTATE_MODE_ENC = 0xC000,
- FFT_ROTATE_MODE_MASK = 0xF000,
+ ROTATE_MODE_ENC = 0xC000,
+ FFT_ROTATE_MODE_MASK = 0xF000,
// QUAD_PERM encodings
- LANE_MASK = 0x3,
- LANE_MAX = LANE_MASK,
- LANE_SHIFT = 2,
- LANE_NUM = 4,
+ LANE_MASK = 0x3,
+ LANE_MAX = LANE_MASK,
+ LANE_SHIFT = 2,
+ LANE_NUM = 4,
// BITMASK_PERM encodings
- BITMASK_MASK = 0x1F,
- BITMASK_MAX = BITMASK_MASK,
- BITMASK_WIDTH = 5,
+ BITMASK_MASK = 0x1F,
+ BITMASK_MAX = BITMASK_MASK,
+ BITMASK_WIDTH = 5,
- BITMASK_AND_SHIFT = 0,
- BITMASK_OR_SHIFT = 5,
- BITMASK_XOR_SHIFT = 10,
+ BITMASK_AND_SHIFT = 0,
+ BITMASK_OR_SHIFT = 5,
+ BITMASK_XOR_SHIFT = 10,
// FFT encodings
- FFT_NO_SWIZZLE = 0x1F,
- FFT_SWIZZLE_00 = 0x0,
- FFT_SWIZZLE_10 = 0x10,
-
- FFT_SWIZZLE_TYPE_MASK = 0x1F,
+ FFT_SWIZZLE_MASK = 0x1F,
+ FFT_SWIZZLE_MAX = 0x1F,
// ROTATE encodings
- ROTATE_MAX_SIZE = 0x1F,
- ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
- ROTATE_DIR_MASK = 0x1,
- ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
+ ROTATE_MAX_SIZE = 0x1F,
+ ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
+ ROTATE_DIR_MASK = 0x1,
+ ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
};
diff --git a/llvm/test/MC/AMDGPU/ds_swizzle.s b/llvm/test/MC/AMDGPU/ds_swizzle.s
index 7d9f5097edbd54..1516c72d625377 100644
--- a/llvm/test/MC/AMDGPU/ds_swizzle.s
+++ b/llvm/test/MC/AMDGPU/ds_swizzle.s
@@ -15,6 +15,10 @@ ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0)
// CHECK: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5)
+// CHECK: [0x05,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: [0x05,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16)
// CHECK: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
@@ -23,11 +27,11 @@ ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31)
// CHECK: [0x1f,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: [0x1f,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
-ds_swizzle_b32 v5, v1 offset:swizzle(FFT,2)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid FFT swizzle type: must be 0, 16, or 31
-
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,32)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid FFT swizzle type: must be 0, 16, or 31
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
+
+ds_swizzle_b32 v5, v1 offset:swizzle(FFT,-2)
+// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT)
// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
>From 742664439bf36bd211f4f41ba31dac8df3233d5a Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Wed, 11 Sep 2024 17:16:26 -0700
Subject: [PATCH 3/6] This commit: (1) disallow the words FFT/ROTATE in
ds_swizzle_b32 for pre-gfx9 targets (2) modify code to align with ISA doc,
namely, if offset >= 0xE000 then it is the FFT mode, and so on.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 10 ++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 22 ++--
llvm/lib/Target/AMDGPU/SIDefines.h | 3 +
llvm/test/MC/AMDGPU/ds_swizzle.s | 108 ++++++++++++------
llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s | 6 +-
llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt | 8 +-
.../MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt | 8 +-
.../MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt | 6 +-
.../Disassembler/AMDGPU/gfx90a_ldst_acc.txt | 6 +-
llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt | 8 +-
10 files changed, 119 insertions(+), 66 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 367d4f68155540..4c27e8cab819d4 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -8146,6 +8146,11 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
using namespace llvm::AMDGPU::Swizzle;
+ if (!AMDGPU::isGFX9Plus(getSTI())) {
+ Error(getLoc(), "FFT mode swizzle not supported on this GPU");
+ return false;
+ }
+
int64_t Swizzle;
SMLoc Loc;
if (!parseSwizzleOperand(Swizzle, 0, FFT_SWIZZLE_MAX,
@@ -8161,6 +8166,11 @@ bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
bool AMDGPUAsmParser::parseSwizzleRotate(int64_t &Imm) {
using namespace llvm::AMDGPU::Swizzle;
+ if (!AMDGPU::isGFX9Plus(getSTI())) {
+ Error(getLoc(), "Rotate mode swizzle not supported on this GPU");
+ return false;
+ }
+
SMLoc Loc;
int64_t Direction;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index ee09d0aeb290ea..104a13018f2399 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1503,8 +1503,21 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
O << " offset:";
- if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
+ // Rotate and FFT modes
+ if (Imm >= ROTATE_MODE_LO && AMDGPU::isGFX9Plus(STI)) {
+ if (Imm >= FFT_MODE_LO) {
+ O << "swizzle(" << IdSymbolic[ID_FFT] << "," << (Imm & FFT_SWIZZLE_MASK)
+ << ")";
+ } else if (Imm >= ROTATE_MODE_LO) {
+ O << "swizzle(" << IdSymbolic[ID_ROTATE] << ","
+ << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ","
+ << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ")";
+ }
+ return;
+ }
+ // Basic mode
+ if ((Imm & QUAD_PERM_ENC_MASK) == QUAD_PERM_ENC) {
O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
for (unsigned I = 0; I < LANE_NUM; ++I) {
O << ",";
@@ -1556,13 +1569,6 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
O << ")";
}
}
- } else if ((Imm & FFT_ROTATE_MODE_MASK) == FFT_MODE_ENC) {
- O << "swizzle(" << IdSymbolic[ID_FFT] << "," << (Imm & FFT_SWIZZLE_MASK)
- << ")";
- } else if ((Imm & FFT_ROTATE_MODE_MASK) == ROTATE_MODE_ENC) {
- O << "swizzle(" << IdSymbolic[ID_ROTATE] << ","
- << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ","
- << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ")";
} else {
printU16ImmDecOperand(MI, OpNo, O);
}
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 30e526da6c250a..9aaadee862fc10 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -861,6 +861,9 @@ enum EncBits : unsigned {
ROTATE_MODE_ENC = 0xC000,
FFT_ROTATE_MODE_MASK = 0xF000,
+ ROTATE_MODE_LO = 0xC000,
+ FFT_MODE_LO = 0xE000,
+
// QUAD_PERM encodings
LANE_MASK = 0x3,
diff --git a/llvm/test/MC/AMDGPU/ds_swizzle.s b/llvm/test/MC/AMDGPU/ds_swizzle.s
index 1516c72d625377..27ecb0d819de9d 100644
--- a/llvm/test/MC/AMDGPU/ds_swizzle.s
+++ b/llvm/test/MC/AMDGPU/ds_swizzle.s
@@ -1,8 +1,12 @@
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=GFX7 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX8 %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR-PREGFX9 %s --implicit-check-not=error:
+// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR-PREGFX9 %s --implicit-check-not=error:
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s 2>&1 | FileCheck -check-prefix=ERROR %s --implicit-check-not=error:
@@ -12,86 +16,116 @@
// FFT mode
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0)
-// CHECK: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5)
-// CHECK: [0x05,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x05,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5) ; encoding: [0x05,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5) ; encoding: [0x05,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16)
-// CHECK: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31)
-// CHECK: [0x1f,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x1f,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0x1f,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0x1f,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:0xf000
+// GFX7: ds_swizzle_b32 v5, v1 offset:61440 ; encoding: [0x00,0xf0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// GFX8: ds_swizzle_b32 v5, v1 offset:61440 ; encoding: [0x00,0xf0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xf0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xf0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,32)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,-2)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: FFT swizzle must be in the interval [0,31]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16,31)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
-
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a closing parentheses
//==============================================================================
// ROTATE mode
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0)
-// CHECK: [0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0)
-// CHECK: [0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1)
-// CHECK: [0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1)
-// CHECK: [0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31)
-// CHECK: [0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31)
-// CHECK: [0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// GFX10PLUS: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:0xd000
+// GFX7: ds_swizzle_b32 v5, v1 offset:53248 ; encoding: [0x00,0xd0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+// GFX8: ds_swizzle_b32 v5, v1 offset:53248 ; encoding: [0x00,0xd0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xd0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xd0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,2,31)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,-1,31)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: direction must be 0 (left) or 1 (right)
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,32)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,-2)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: number of threads to rotate must be in the interval [0,31]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a comma
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1,2)
-// ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
-
-
-
-
+// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
+// ERROR: :[[@LINE-2]]:{{[0-9]+}}: error: expected a closing parentheses
diff --git a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
index ee8218613a6dc6..0b518acc884df0 100644
--- a/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
+++ b/llvm/test/MC/AMDGPU/gfx90a_ldst_acc.s
@@ -8257,15 +8257,15 @@ ds_read_u16 a5, v1
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
ds_read_u16 a5, v1 offset:4
-// GFX90A: ds_swizzle_b32 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05]
+// GFX90A: ds_swizzle_b32 a5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05]
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
ds_swizzle_b32 a5, v1 offset:65535
-// GFX90A: ds_swizzle_b32 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff]
+// GFX90A: ds_swizzle_b32 a255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff]
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
ds_swizzle_b32 a255, v1 offset:65535
-// GFX90A: ds_swizzle_b32 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05]
+// GFX90A: ds_swizzle_b32 a5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05]
// NOT-GFX90A: :[[@LINE+1]]:{{[0-9]+}}: error: invalid register class: agpr loads and stores not supported on this GPU
ds_swizzle_b32 a5, v255 offset:65535
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
index 688b5f916630af..2bd0fe8b0b0724 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
@@ -4208,22 +4208,22 @@
# GFX10: ds_sub_u64 v255, v[2:3] offset:65535 ; encoding: [0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00]
0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00
-# GFX10: ds_swizzle_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
+# GFX10: ds_swizzle_b32 v255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff
# GFX10: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05
-# GFX10: ds_swizzle_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05
-# GFX10: ds_swizzle_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) gds ; encoding: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05
# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(BITMASK_PERM,"00p00") ; encoding: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05
-# GFX10: ds_swizzle_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
+# GFX10: ds_swizzle_b32 v5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05
# GFX10: ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 ; encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
index 1b632b56400fbc..a615ff97615f67 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
@@ -3802,16 +3802,16 @@
# GFX11: ds_sub_u64 v255, v[2:3] offset:65535 ; encoding: [0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00]
0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00
-# GFX11: ds_swizzle_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
+# GFX11: ds_swizzle_b32 v255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff
# GFX11: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05
-# GFX11: ds_swizzle_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05
-# GFX11: ds_swizzle_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) gds ; encoding: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05
# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(BITMASK_PERM,"00p00") ; encoding: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
@@ -3829,7 +3829,7 @@
# GFX11: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1) ; encoding: [0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08
-# GFX11: ds_swizzle_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
+# GFX11: ds_swizzle_b32 v5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05
# GFX11: ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 ; encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
index 473ede00603a78..9ba3875043f1ac 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
@@ -2415,13 +2415,13 @@
# GFX12: ds_sub_u64 v255, v[2:3] offset:65535 ; encoding: [0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00]
0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00
-# GFX12: ds_swizzle_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
+# GFX12: ds_swizzle_b32 v255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff
# GFX12: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05
-# GFX12: ds_swizzle_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05
# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(BITMASK_PERM,"00p00") ; encoding: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
@@ -2439,7 +2439,7 @@
# GFX12: ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,32,1) ; encoding: [0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
0x20,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08
-# GFX12: ds_swizzle_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
+# GFX12: ds_swizzle_b32 v5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05
# GFX12: ds_store_2addr_b32 v0, v1, v2 ; encoding: [0x00,0x00,0x38,0xd8,0x00,0x01,0x02,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
index b8cc7ac604da2f..081b40ac78f8c1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx90a_ldst_acc.txt
@@ -6192,13 +6192,13 @@
# GFX90A: ds_read_u16 a5, v1 offset:4 ; encoding: [0x04,0x00,0x78,0xda,0x01,0x00,0x00,0x05]
0x04,0x00,0x78,0xda,0x01,0x00,0x00,0x05
-# GFX90A: ds_swizzle_b32 a5, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05]
+# GFX90A: ds_swizzle_b32 a5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05]
0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0x05
-# GFX90A: ds_swizzle_b32 a255, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff]
+# GFX90A: ds_swizzle_b32 a255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff]
0xff,0xff,0x7a,0xda,0x01,0x00,0x00,0xff
-# GFX90A: ds_swizzle_b32 a5, v255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05]
+# GFX90A: ds_swizzle_b32 a5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05]
0xff,0xff,0x7a,0xda,0xff,0x00,0x00,0x05
# GFX90A: ds_swizzle_b32 a5, v1 ; encoding: [0x00,0x00,0x7a,0xda,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
index 58a44e1250542f..f526f23ba2ac6a 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
@@ -1074,13 +1074,13 @@
# CHECK: ds_read_u16 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05
-# CHECK: ds_swizzle_b32 v5, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05]
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05
-# CHECK: ds_swizzle_b32 v255, v1 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff]
+# CHECK: ds_swizzle_b32 v255, v1 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff]
0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff
-# CHECK: ds_swizzle_b32 v5, v255 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05]
+# CHECK: ds_swizzle_b32 v5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05
# CHECK: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
@@ -1089,7 +1089,7 @@
# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(BITMASK_PERM,"00p00") ; encoding: [0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05
-# CHECK: ds_swizzle_b32 v5, v1 offset:65535 gds ; encoding: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) gds ; encoding: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05
# CHECK: ds_permute_b32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05]
>From 3b6c5d985dc19dac8e731c8af454c521ae8821f6 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Thu, 12 Sep 2024 15:15:44 -0700
Subject: [PATCH 4/6] This commit: (1) for parseSwizzleOperand(), change the
type of ErrMsg from StringRef to Twine (2) change some single-char string to
single quotes (3) undo some changes by clang-format.
---
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 8 +--
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 10 ++--
llvm/lib/Target/AMDGPU/SIDefines.h | 50 +++++++++----------
.../Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 9 +++-
4 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 4c27e8cab819d4..50b3e59cfcb85e 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1829,7 +1829,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool parseSwizzleOperand(int64_t &Op,
const unsigned MinVal,
const unsigned MaxVal,
- const StringRef ErrMsg,
+ const Twine ErrMsg,
SMLoc &Loc);
bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
const unsigned MinVal,
@@ -7977,7 +7977,7 @@ bool
AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,
const unsigned MinVal,
const unsigned MaxVal,
- const StringRef ErrMsg,
+ const Twine ErrMsg,
SMLoc &Loc) {
if (!skipToken(AsmToken::Comma, "expected a comma")) {
return false;
@@ -8155,7 +8155,7 @@ bool AMDGPUAsmParser::parseSwizzleFFT(int64_t &Imm) {
SMLoc Loc;
if (!parseSwizzleOperand(Swizzle, 0, FFT_SWIZZLE_MAX,
"FFT swizzle must be in the interval [0," +
- Twine(FFT_SWIZZLE_MAX).str() + Twine(']').str(),
+ Twine(FFT_SWIZZLE_MAX) + Twine(']'),
Loc))
return false;
@@ -8182,7 +8182,7 @@ bool AMDGPUAsmParser::parseSwizzleRotate(int64_t &Imm) {
if (!parseSwizzleOperand(
RotateSize, 0, ROTATE_MAX_SIZE,
"number of threads to rotate must be in the interval [0," +
- Twine(ROTATE_MAX_SIZE).str() + Twine(']').str(),
+ Twine(ROTATE_MAX_SIZE) + Twine(']'),
Loc))
return false;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 104a13018f2399..91e8f52df5b41d 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1506,12 +1506,12 @@ void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
// Rotate and FFT modes
if (Imm >= ROTATE_MODE_LO && AMDGPU::isGFX9Plus(STI)) {
if (Imm >= FFT_MODE_LO) {
- O << "swizzle(" << IdSymbolic[ID_FFT] << "," << (Imm & FFT_SWIZZLE_MASK)
- << ")";
+ O << "swizzle(" << IdSymbolic[ID_FFT] << ',' << (Imm & FFT_SWIZZLE_MASK)
+ << ')';
} else if (Imm >= ROTATE_MODE_LO) {
- O << "swizzle(" << IdSymbolic[ID_ROTATE] << ","
- << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ","
- << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ")";
+ O << "swizzle(" << IdSymbolic[ID_ROTATE] << ','
+ << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ','
+ << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ')';
}
return;
}
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 9aaadee862fc10..fc902159d177fa 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -850,48 +850,48 @@ enum EncBits : unsigned {
// swizzle mode encodings
- QUAD_PERM_ENC = 0x8000,
- QUAD_PERM_ENC_MASK = 0xFF00,
+ QUAD_PERM_ENC = 0x8000,
+ QUAD_PERM_ENC_MASK = 0xFF00,
- BITMASK_PERM_ENC = 0x0000,
+ BITMASK_PERM_ENC = 0x0000,
BITMASK_PERM_ENC_MASK = 0x8000,
- FFT_MODE_ENC = 0xE000,
+ FFT_MODE_ENC = 0xE000,
- ROTATE_MODE_ENC = 0xC000,
- FFT_ROTATE_MODE_MASK = 0xF000,
+ ROTATE_MODE_ENC = 0xC000,
+ FFT_ROTATE_MODE_MASK = 0xF000,
- ROTATE_MODE_LO = 0xC000,
- FFT_MODE_LO = 0xE000,
+ ROTATE_MODE_LO = 0xC000,
+ FFT_MODE_LO = 0xE000,
// QUAD_PERM encodings
- LANE_MASK = 0x3,
- LANE_MAX = LANE_MASK,
- LANE_SHIFT = 2,
- LANE_NUM = 4,
+ LANE_MASK = 0x3,
+ LANE_MAX = LANE_MASK,
+ LANE_SHIFT = 2,
+ LANE_NUM = 4,
// BITMASK_PERM encodings
- BITMASK_MASK = 0x1F,
- BITMASK_MAX = BITMASK_MASK,
- BITMASK_WIDTH = 5,
+ BITMASK_MASK = 0x1F,
+ BITMASK_MAX = BITMASK_MASK,
+ BITMASK_WIDTH = 5,
- BITMASK_AND_SHIFT = 0,
- BITMASK_OR_SHIFT = 5,
- BITMASK_XOR_SHIFT = 10,
+ BITMASK_AND_SHIFT = 0,
+ BITMASK_OR_SHIFT = 5,
+ BITMASK_XOR_SHIFT = 10,
// FFT encodings
- FFT_SWIZZLE_MASK = 0x1F,
- FFT_SWIZZLE_MAX = 0x1F,
+ FFT_SWIZZLE_MASK = 0x1F,
+ FFT_SWIZZLE_MAX = 0x1F,
// ROTATE encodings
- ROTATE_MAX_SIZE = 0x1F,
- ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
- ROTATE_DIR_MASK = 0x1,
- ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
- ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
+ ROTATE_MAX_SIZE = 0x1F,
+ ROTATE_DIR_SHIFT = 10, // bit position of rotate direction
+ ROTATE_DIR_MASK = 0x1,
+ ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
+ ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
};
} // namespace Swizzle
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
index 702a0d6118bbae..b1e8bf07ff576a 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
@@ -647,8 +647,13 @@ namespace Swizzle {
// This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
const char *const IdSymbolic[] = {
- "QUAD_PERM", "BITMASK_PERM", "SWAP", "REVERSE",
- "BROADCAST", "FFT", "ROTATE",
+ "QUAD_PERM",
+ "BITMASK_PERM",
+ "SWAP",
+ "REVERSE",
+ "BROADCAST",
+ "FFT",
+ "ROTATE",
};
} // namespace Swizzle
>From 7af446de54f9bbb12a06f0957c71b6b28809f298 Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Fri, 13 Sep 2024 14:41:34 -0700
Subject: [PATCH 5/6] For function parseSwizzleOperand(), change type of ErrMsg
from const Twine to const Twine&. Also add "clang-format off" to prevent
clang-format make unwanted format changes.
---
.../Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 15 +++++----------
llvm/lib/Target/AMDGPU/SIDefines.h | 2 ++
llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 2 ++
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 50b3e59cfcb85e..e38b97cba22482 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1826,10 +1826,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
ParseStatus parseSOPPBrTarget(OperandVector &Operands);
ParseStatus parseBoolReg(OperandVector &Operands);
- bool parseSwizzleOperand(int64_t &Op,
- const unsigned MinVal,
- const unsigned MaxVal,
- const Twine ErrMsg,
+ bool parseSwizzleOperand(int64_t &Op, const unsigned MinVal,
+ const unsigned MaxVal, const Twine &ErrMsg,
SMLoc &Loc);
bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
const unsigned MinVal,
@@ -7973,12 +7971,9 @@ encodeBitmaskPerm(const unsigned AndMask,
(XorMask << BITMASK_XOR_SHIFT);
}
-bool
-AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,
- const unsigned MinVal,
- const unsigned MaxVal,
- const Twine ErrMsg,
- SMLoc &Loc) {
+bool AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op, const unsigned MinVal,
+ const unsigned MaxVal,
+ const Twine &ErrMsg, SMLoc &Loc) {
if (!skipToken(AsmToken::Comma, "expected a comma")) {
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index fc902159d177fa..07c80bd2575f0e 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -846,6 +846,7 @@ enum Id : unsigned { // id of symbolic names
ID_ROTATE
};
+// clang-format off
enum EncBits : unsigned {
// swizzle mode encodings
@@ -893,6 +894,7 @@ enum EncBits : unsigned {
ROTATE_SIZE_SHIFT = 5, // bit position of rotate size
ROTATE_SIZE_MASK = ROTATE_MAX_SIZE,
};
+// clang-format on
} // namespace Swizzle
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
index b1e8bf07ff576a..a8e4ce133ffbc8 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp
@@ -645,6 +645,7 @@ unsigned const DfmtNfmt2UFmtGFX11[] = {
namespace Swizzle {
+// clang-format off
// This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
const char *const IdSymbolic[] = {
"QUAD_PERM",
@@ -655,6 +656,7 @@ const char *const IdSymbolic[] = {
"FFT",
"ROTATE",
};
+// clang-format on
} // namespace Swizzle
>From 6f716a85d5b4a98f958ced69e427b812dbac06cd Mon Sep 17 00:00:00 2001
From: Jun Wang <jwang86 at yahoo.com>
Date: Mon, 16 Sep 2024 15:10:04 -0700
Subject: [PATCH 6/6] Update tests.
---
llvm/test/MC/AMDGPU/ds_swizzle.s | 26 +++++++++----------
llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt | 24 +++++++++++++++++
.../MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt | 24 +++++++++++++++++
.../MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt | 24 +++++++++++++++++
llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt | 24 +++++++++++++++++
5 files changed, 109 insertions(+), 13 deletions(-)
diff --git a/llvm/test/MC/AMDGPU/ds_swizzle.s b/llvm/test/MC/AMDGPU/ds_swizzle.s
index 27ecb0d819de9d..d768339fe5b77e 100644
--- a/llvm/test/MC/AMDGPU/ds_swizzle.s
+++ b/llvm/test/MC/AMDGPU/ds_swizzle.s
@@ -1,6 +1,6 @@
// RUN: not llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck -check-prefix=GFX7 %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=GFX8 %s
-// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx908 -show-encoding %s | FileCheck -check-prefix=GFX9 %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck -check-prefix=GFX10PLUS %s
@@ -17,28 +17,28 @@
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5) ; encoding: [0x05,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5) ; encoding: [0x05,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,5) ; encoding: [0x05,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: FFT mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0x1f,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0x1f,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) ; encoding: [0x1f,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:0xf000
// GFX7: ds_swizzle_b32 v5, v1 offset:61440 ; encoding: [0x00,0xf0,0xd4,0xd8,0x01,0x00,0x00,0x05]
// GFX8: ds_swizzle_b32 v5, v1 offset:61440 ; encoding: [0x00,0xf0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xf0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xf0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xf0,0xd4,0xd8,0x01,0x00,0x00,0x05]
@@ -63,38 +63,38 @@ ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16,31)
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31)
// ERROR-PREGFX9: :[[@LINE-1]]:{{[0-9]+}}: error: Rotate mode swizzle not supported on this GPU
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
ds_swizzle_b32 v5, v1 offset:0xd000
// GFX7: ds_swizzle_b32 v5, v1 offset:53248 ; encoding: [0x00,0xd0,0xd4,0xd8,0x01,0x00,0x00,0x05]
// GFX8: ds_swizzle_b32 v5, v1 offset:53248 ; encoding: [0x00,0xd0,0x7a,0xd8,0x01,0x00,0x00,0x05]
-// CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xd0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+// GFX9: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xd0,0x7a,0xd8,0x01,0x00,0x00,0x05]
// GFX10PLUS: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xd0,0xd4,0xd8,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
index 2bd0fe8b0b0724..bf9bad5240416d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_ds.txt
@@ -4226,6 +4226,30 @@
# GFX10: ds_swizzle_b32 v5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX10: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05
+
# GFX10: ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 ; encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
index a615ff97615f67..448cfc95de0950 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_ds.txt
@@ -3832,6 +3832,30 @@
# GFX11: ds_swizzle_b32 v5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX11: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05
+
# GFX11: ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535 ; encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
index 9ba3875043f1ac..080a4cab2a319d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
@@ -2442,6 +2442,30 @@
# GFX12: ds_swizzle_b32 v5, v255 offset:swizzle(FFT,31) ; encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x10,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xe0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc0,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc4,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc3,0xd4,0xd8,0x01,0x00,0x00,0x05
+
+# GFX12: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc7,0xd4,0xd8,0x01,0x00,0x00,0x05
+
# GFX12: ds_store_2addr_b32 v0, v1, v2 ; encoding: [0x00,0x00,0x38,0xd8,0x00,0x01,0x02,0x00]
0x00,0x00,0x38,0xd8,0x00,0x01,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
index f526f23ba2ac6a..2af4b8396d71a4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_ds.txt
@@ -1092,6 +1092,30 @@
# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,31) gds ; encoding: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,16) ; encoding: [0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0x10,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05
+
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(FFT,0) ; encoding: [0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xe0,0x7a,0xd8,0x01,0x00,0x00,0x05
+
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,0) ; encoding: [0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05
+
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,0) ; encoding: [0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0x00,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05
+
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,1) ; encoding: [0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc0,0x7a,0xd8,0x01,0x00,0x00,0x05
+
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,1) ; encoding: [0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0x20,0xc4,0x7a,0xd8,0x01,0x00,0x00,0x05
+
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,0,31) ; encoding: [0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc3,0x7a,0xd8,0x01,0x00,0x00,0x05
+
+# CHECK: ds_swizzle_b32 v5, v1 offset:swizzle(ROTATE,1,31) ; encoding: [0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05]
+0xe0,0xc7,0x7a,0xd8,0x01,0x00,0x00,0x05
+
# CHECK: ds_permute_b32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05]
0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05
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