[llvm] [RISCV] Add scheduling model for Syntacore SCR7 (PR #108814)

[Michael Maitland via llvm-commits]

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@@ -0,0 +1,378 @@
+//==- RISCVSchedSyntacoreSCR7.td - Syntacore SCR7 Sched Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+// This file covers scheduling model for rv64imafdc_zba_zbb_zbc_zbs
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michaelmaitland wrote:

According to 108406 I think this processor is rv64imafdcv_zba_zbb_zbc_zbs_zkn. Are we missing `v` and `zkn` here?

https://github.com/llvm/llvm-project/pull/108814