[llvm] 823eab2 - [AArch64] Add a selection for vector scmp/ucmp tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 16 06:25:20 PDT 2024
Author: David Green
Date: 2024-09-16T14:25:15+01:00
New Revision: 823eab2bd5fcdade92790d0f53fc5978ae068e46
URL: https://github.com/llvm/llvm-project/commit/823eab2bd5fcdade92790d0f53fc5978ae068e46
DIFF: https://github.com/llvm/llvm-project/commit/823eab2bd5fcdade92790d0f53fc5978ae068e46.diff
LOG: [AArch64] Add a selection for vector scmp/ucmp tests. NFC
Added:
llvm/test/CodeGen/AArch64/sve-scmp.ll
llvm/test/CodeGen/AArch64/sve-ucmp.ll
Modified:
llvm/test/CodeGen/AArch64/scmp.ll
llvm/test/CodeGen/AArch64/ucmp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/scmp.ll b/llvm/test/CodeGen/AArch64/scmp.ll
index bcad1c1a11aa72..3d18a904ed2d3f 100644
--- a/llvm/test/CodeGen/AArch64/scmp.ll
+++ b/llvm/test/CodeGen/AArch64/scmp.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @scmp.8.8(i8 %x, i8 %y) nounwind {
; CHECK-SD-LABEL: scmp.8.8:
@@ -132,3 +132,416 @@ define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {
%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
ret i64 %1
}
+
+define <8 x i8> @s_v8i8(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-SD-LABEL: s_v8i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8b, #1
+; CHECK-SD-NEXT: cmgt v3.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: cmgt v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: and v1.8b, v3.8b, v2.8b
+; CHECK-SD-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8b, #1
+; CHECK-GI-NEXT: cmgt v3.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
+; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <8 x i8> @llvm.scmp(<8 x i8> %a, <8 x i8> %b)
+ ret <8 x i8> %c
+}
+
+define <16 x i8> @s_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: s_v16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.16b, #1
+; CHECK-SD-NEXT: cmgt v3.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: cmgt v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: and v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.16b, #1
+; CHECK-GI-NEXT: cmgt v3.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <16 x i8> @llvm.scmp(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %c
+}
+
+define <4 x i16> @s_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-SD-LABEL: s_v4i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4h, #1
+; CHECK-SD-NEXT: cmgt v3.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: cmgt v0.4h, v1.4h, v0.4h
+; CHECK-SD-NEXT: and v1.8b, v3.8b, v2.8b
+; CHECK-SD-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v4i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #1
+; CHECK-GI-NEXT: cmgt v3.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
+; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <4 x i16> @llvm.scmp(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %c
+}
+
+define <8 x i16> @s_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-SD-LABEL: s_v8i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #1
+; CHECK-SD-NEXT: cmgt v3.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: cmgt v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: and v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v8i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8h, #1
+; CHECK-GI-NEXT: cmgt v3.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <8 x i16> @llvm.scmp(<8 x i16> %a, <8 x i16> %b)
+ ret <8 x i16> %c
+}
+
+define <16 x i16> @s_v16i16(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: s_v16i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v4.8h, #1
+; CHECK-SD-NEXT: cmgt v5.8h, v0.8h, v2.8h
+; CHECK-SD-NEXT: cmgt v6.8h, v1.8h, v3.8h
+; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h
+; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h
+; CHECK-SD-NEXT: and v2.16b, v5.16b, v4.16b
+; CHECK-SD-NEXT: and v3.16b, v6.16b, v4.16b
+; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v16i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v4.8h, #1
+; CHECK-GI-NEXT: cmgt v5.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: cmgt v6.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h
+; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h
+; CHECK-GI-NEXT: and v5.16b, v4.16b, v5.16b
+; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b
+; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v5.16b
+; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v4.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <16 x i16> @llvm.scmp(<16 x i16> %a, <16 x i16> %b)
+ ret <16 x i16> %c
+}
+
+define <2 x i32> @s_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-SD-LABEL: s_v2i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2s, #1
+; CHECK-SD-NEXT: cmgt v3.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-SD-NEXT: and v1.8b, v3.8b, v2.8b
+; CHECK-SD-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #1
+; CHECK-GI-NEXT: cmgt v3.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
+; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <2 x i32> @llvm.scmp(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %c
+}
+
+define <4 x i32> @s_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-SD-LABEL: s_v4i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #1
+; CHECK-SD-NEXT: cmgt v3.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: and v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v4i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: cmgt v3.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <4 x i32> @llvm.scmp(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %c
+}
+
+define <8 x i32> @s_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; CHECK-SD-LABEL: s_v8i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v4.4s, #1
+; CHECK-SD-NEXT: cmgt v5.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT: cmgt v6.4s, v1.4s, v3.4s
+; CHECK-SD-NEXT: cmgt v0.4s, v2.4s, v0.4s
+; CHECK-SD-NEXT: cmgt v1.4s, v3.4s, v1.4s
+; CHECK-SD-NEXT: and v2.16b, v5.16b, v4.16b
+; CHECK-SD-NEXT: and v3.16b, v6.16b, v4.16b
+; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v8i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v4.4s, #1
+; CHECK-GI-NEXT: cmgt v5.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: cmgt v6.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.4s, v2.4s, v0.4s
+; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v1.4s
+; CHECK-GI-NEXT: and v5.16b, v4.16b, v5.16b
+; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b
+; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v5.16b
+; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v4.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <8 x i32> @llvm.scmp(<8 x i32> %a, <8 x i32> %b)
+ ret <8 x i32> %c
+}
+
+define <2 x i64> @s_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-SD-LABEL: s_v2i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: cmgt v0.2d, v1.2d, v0.2d
+; CHECK-SD-NEXT: dup v3.2d, x8
+; CHECK-SD-NEXT: and v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v2i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI16_0
+; CHECK-GI-NEXT: cmgt v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI16_0]
+; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <2 x i64> @llvm.scmp(<2 x i64> %a, <2 x i64> %b)
+ ret <2 x i64> %c
+}
+
+define <4 x i64> @s_v4i64(<4 x i64> %a, <4 x i64> %b) {
+; CHECK-SD-LABEL: s_v4i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-SD-NEXT: cmgt v6.2d, v1.2d, v3.2d
+; CHECK-SD-NEXT: dup v5.2d, x8
+; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d
+; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d
+; CHECK-SD-NEXT: and v2.16b, v4.16b, v5.16b
+; CHECK-SD-NEXT: and v3.16b, v6.16b, v5.16b
+; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: s_v4i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-GI-NEXT: cmgt v6.2d, v1.2d, v3.2d
+; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d
+; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d
+; CHECK-GI-NEXT: and v4.16b, v5.16b, v4.16b
+; CHECK-GI-NEXT: and v5.16b, v5.16b, v6.16b
+; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v4.16b
+; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v5.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <4 x i64> @llvm.scmp(<4 x i64> %a, <4 x i64> %b)
+ ret <4 x i64> %c
+}
+
+define <16 x i8> @signOf_neon_scmp(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_lo, <8 x i16> %s1_hi) {
+; CHECK-SD-LABEL: signOf_neon_scmp:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: cmgt v5.8h, v0.8h, v2.8h
+; CHECK-SD-NEXT: cmgt v2.8h, v2.8h, v0.8h
+; CHECK-SD-NEXT: cmgt v4.8h, v1.8h, v3.8h
+; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h
+; CHECK-SD-NEXT: umov w8, v5.h[1]
+; CHECK-SD-NEXT: umov w9, v2.h[1]
+; CHECK-SD-NEXT: umov w10, v5.h[0]
+; CHECK-SD-NEXT: umov w11, v2.h[0]
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst w9, #0xffff
+; CHECK-SD-NEXT: csinv w8, w8, wzr, eq
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v5.h[2]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w11, #0xffff
+; CHECK-SD-NEXT: umov w11, v2.h[2]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: fmov s0, w9
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[3]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w11, #0xffff
+; CHECK-SD-NEXT: mov v0.b[1], w8
+; CHECK-SD-NEXT: umov w8, v5.h[3]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[2], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v5.h[4]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[4]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[3], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v5.h[5]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[5]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[4], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v5.h[6]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[6]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[5], w9
+; CHECK-SD-NEXT: umov w9, v5.h[7]
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[7]
+; CHECK-SD-NEXT: csinv w8, w8, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[6], w8
+; CHECK-SD-NEXT: tst w9, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[0]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[0]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[7], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[1]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[1]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[8], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[2]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[2]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[9], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[3]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[3]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[10], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[4]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[4]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[11], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[5]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[5]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[12], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[6]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[6]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[13], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[7]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[7]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[14], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: csinv w8, w8, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[15], w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signOf_neon_scmp:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: cmgt v4.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: cmgt v5.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h
+; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h
+; CHECK-GI-NEXT: movi v2.16b, #1
+; CHECK-GI-NEXT: movi v3.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: uzp1 v4.16b, v4.16b, v5.16b
+; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: shl v1.16b, v4.16b, #7
+; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
+; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7
+; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
+; CHECK-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: bsl v0.16b, v3.16b, v1.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i16> %s0_lo, <8 x i16> %s0_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %1 = shufflevector <8 x i16> %s1_lo, <8 x i16> %s1_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %or.i = tail call <16 x i8> @llvm.scmp.v16i8.v16i16(<16 x i16> %0, <16 x i16> %1)
+ ret <16 x i8> %or.i
+}
diff --git a/llvm/test/CodeGen/AArch64/sve-scmp.ll b/llvm/test/CodeGen/AArch64/sve-scmp.ll
new file mode 100644
index 00000000000000..2083ddd8c38377
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-scmp.ll
@@ -0,0 +1,160 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+
+define <vscale x 8 x i8> @s_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
+; CHECK-LABEL: s_nxv8i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: sxtb z0.h, p0/m, z0.h
+; CHECK-NEXT: sxtb z1.h, p0/m, z1.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.h, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 8 x i8> @llvm.scmp(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b)
+ ret <vscale x 8 x i8> %c
+}
+
+define <vscale x 16 x i8> @s_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: s_nxv16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmpgt p1.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: cmpgt p0.b, p0/z, z1.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.b, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 16 x i8> @llvm.scmp(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
+ ret <vscale x 16 x i8> %c
+}
+
+define <vscale x 4 x i16> @s_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
+; CHECK-LABEL: s_nxv4i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: sxth z0.s, p0/m, z0.s
+; CHECK-NEXT: sxth z1.s, p0/m, z1.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 4 x i16> @llvm.scmp(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b)
+ ret <vscale x 4 x i16> %c
+}
+
+define <vscale x 8 x i16> @s_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: s_nxv8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.h, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 8 x i16> @llvm.scmp(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
+ ret <vscale x 8 x i16> %c
+}
+
+define <vscale x 16 x i16> @s_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
+; CHECK-LABEL: s_nxv16i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmpgt p1.h, p0/z, z0.h, z2.h
+; CHECK-NEXT: cmpgt p2.h, p0/z, z1.h, z3.h
+; CHECK-NEXT: cmpgt p3.h, p0/z, z2.h, z0.h
+; CHECK-NEXT: cmpgt p0.h, p0/z, z3.h, z1.h
+; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z1.h, p2/z, #1 // =0x1
+; CHECK-NEXT: mov z0.h, p3/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z1.h, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 16 x i16> @llvm.scmp(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b)
+ ret <vscale x 16 x i16> %c
+}
+
+define <vscale x 2 x i32> @s_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+; CHECK-LABEL: s_nxv2i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: sxtw z0.d, p0/m, z0.d
+; CHECK-NEXT: sxtw z1.d, p0/m, z1.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 2 x i32> @llvm.scmp(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+ ret <vscale x 2 x i32> %c
+}
+
+define <vscale x 4 x i32> @s_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: s_nxv4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 4 x i32> @llvm.scmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
+ ret <vscale x 4 x i32> %c
+}
+
+define <vscale x 8 x i32> @s_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
+; CHECK-LABEL: s_nxv8i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmpgt p1.s, p0/z, z0.s, z2.s
+; CHECK-NEXT: cmpgt p2.s, p0/z, z1.s, z3.s
+; CHECK-NEXT: cmpgt p3.s, p0/z, z2.s, z0.s
+; CHECK-NEXT: cmpgt p0.s, p0/z, z3.s, z1.s
+; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z1.s, p2/z, #1 // =0x1
+; CHECK-NEXT: mov z0.s, p3/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 8 x i32> @llvm.scmp(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b)
+ ret <vscale x 8 x i32> %c
+}
+
+define <vscale x 2 x i64> @s_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: s_nxv2i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 2 x i64> @llvm.scmp(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+ ret <vscale x 2 x i64> %c
+}
+
+define <vscale x 4 x i64> @s_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
+; CHECK-LABEL: s_nxv4i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmpgt p1.d, p0/z, z0.d, z2.d
+; CHECK-NEXT: cmpgt p2.d, p0/z, z1.d, z3.d
+; CHECK-NEXT: cmpgt p3.d, p0/z, z2.d, z0.d
+; CHECK-NEXT: cmpgt p0.d, p0/z, z3.d, z1.d
+; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z1.d, p2/z, #1 // =0x1
+; CHECK-NEXT: mov z0.d, p3/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 4 x i64> @llvm.scmp(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
+ ret <vscale x 4 x i64> %c
+}
diff --git a/llvm/test/CodeGen/AArch64/sve-ucmp.ll b/llvm/test/CodeGen/AArch64/sve-ucmp.ll
new file mode 100644
index 00000000000000..0ee31821e56ef9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-ucmp.ll
@@ -0,0 +1,160 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s
+
+define <vscale x 8 x i8> @u_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
+; CHECK-LABEL: u_nxv8i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: and z0.h, z0.h, #0xff
+; CHECK-NEXT: and z1.h, z1.h, #0xff
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmphi p1.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: cmphi p0.h, p0/z, z1.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.h, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 8 x i8> @llvm.ucmp(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b)
+ ret <vscale x 8 x i8> %c
+}
+
+define <vscale x 16 x i8> @u_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
+; CHECK-LABEL: u_nxv16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.b
+; CHECK-NEXT: cmphi p1.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: cmphi p0.b, p0/z, z1.b, z0.b
+; CHECK-NEXT: mov z0.b, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.b, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 16 x i8> @llvm.ucmp(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
+ ret <vscale x 16 x i8> %c
+}
+
+define <vscale x 4 x i16> @u_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
+; CHECK-LABEL: u_nxv4i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: and z0.s, z0.s, #0xffff
+; CHECK-NEXT: and z1.s, z1.s, #0xffff
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmphi p1.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: cmphi p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 4 x i16> @llvm.ucmp(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b)
+ ret <vscale x 4 x i16> %c
+}
+
+define <vscale x 8 x i16> @u_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
+; CHECK-LABEL: u_nxv8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmphi p1.h, p0/z, z0.h, z1.h
+; CHECK-NEXT: cmphi p0.h, p0/z, z1.h, z0.h
+; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.h, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 8 x i16> @llvm.ucmp(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
+ ret <vscale x 8 x i16> %c
+}
+
+define <vscale x 16 x i16> @u_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
+; CHECK-LABEL: u_nxv16i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.h
+; CHECK-NEXT: cmphi p1.h, p0/z, z0.h, z2.h
+; CHECK-NEXT: cmphi p2.h, p0/z, z1.h, z3.h
+; CHECK-NEXT: cmphi p3.h, p0/z, z2.h, z0.h
+; CHECK-NEXT: cmphi p0.h, p0/z, z3.h, z1.h
+; CHECK-NEXT: mov z0.h, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z1.h, p2/z, #1 // =0x1
+; CHECK-NEXT: mov z0.h, p3/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z1.h, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 16 x i16> @llvm.ucmp(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b)
+ ret <vscale x 16 x i16> %c
+}
+
+define <vscale x 2 x i32> @u_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
+; CHECK-LABEL: u_nxv2i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: and z0.d, z0.d, #0xffffffff
+; CHECK-NEXT: and z1.d, z1.d, #0xffffffff
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmphi p1.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: cmphi p0.d, p0/z, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 2 x i32> @llvm.ucmp(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+ ret <vscale x 2 x i32> %c
+}
+
+define <vscale x 4 x i32> @u_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: u_nxv4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmphi p1.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: cmphi p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 4 x i32> @llvm.ucmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
+ ret <vscale x 4 x i32> %c
+}
+
+define <vscale x 8 x i32> @u_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
+; CHECK-LABEL: u_nxv8i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: cmphi p1.s, p0/z, z0.s, z2.s
+; CHECK-NEXT: cmphi p2.s, p0/z, z1.s, z3.s
+; CHECK-NEXT: cmphi p3.s, p0/z, z2.s, z0.s
+; CHECK-NEXT: cmphi p0.s, p0/z, z3.s, z1.s
+; CHECK-NEXT: mov z0.s, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z1.s, p2/z, #1 // =0x1
+; CHECK-NEXT: mov z0.s, p3/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z1.s, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 8 x i32> @llvm.ucmp(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b)
+ ret <vscale x 8 x i32> %c
+}
+
+define <vscale x 2 x i64> @u_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
+; CHECK-LABEL: u_nxv2i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmphi p1.d, p0/z, z0.d, z1.d
+; CHECK-NEXT: cmphi p0.d, p0/z, z1.d, z0.d
+; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z0.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 2 x i64> @llvm.ucmp(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
+ ret <vscale x 2 x i64> %c
+}
+
+define <vscale x 4 x i64> @u_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
+; CHECK-LABEL: u_nxv4i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ptrue p0.d
+; CHECK-NEXT: cmphi p1.d, p0/z, z0.d, z2.d
+; CHECK-NEXT: cmphi p2.d, p0/z, z1.d, z3.d
+; CHECK-NEXT: cmphi p3.d, p0/z, z2.d, z0.d
+; CHECK-NEXT: cmphi p0.d, p0/z, z3.d, z1.d
+; CHECK-NEXT: mov z0.d, p1/z, #1 // =0x1
+; CHECK-NEXT: mov z1.d, p2/z, #1 // =0x1
+; CHECK-NEXT: mov z0.d, p3/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: mov z1.d, p0/m, #-1 // =0xffffffffffffffff
+; CHECK-NEXT: ret
+entry:
+ %c = call <vscale x 4 x i64> @llvm.ucmp(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
+ ret <vscale x 4 x i64> %c
+}
diff --git a/llvm/test/CodeGen/AArch64/ucmp.ll b/llvm/test/CodeGen/AArch64/ucmp.ll
index 1a7f0be11cee62..7e94cb6c103b52 100644
--- a/llvm/test/CodeGen/AArch64/ucmp.ll
+++ b/llvm/test/CodeGen/AArch64/ucmp.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i8 @ucmp.8.8(i8 %x, i8 %y) nounwind {
; CHECK-SD-LABEL: ucmp.8.8:
@@ -172,3 +172,416 @@ define <1 x i64> @ucmp.1.64.65(<1 x i65> %x, <1 x i65> %y) {
%1 = call <1 x i64> @llvm.ucmp(<1 x i65> %x, <1 x i65> %y)
ret <1 x i64> %1
}
+
+define <8 x i8> @u_v8i8(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-SD-LABEL: u_v8i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8b, #1
+; CHECK-SD-NEXT: cmhi v3.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: cmhi v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: and v1.8b, v3.8b, v2.8b
+; CHECK-SD-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v8i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8b, #1
+; CHECK-GI-NEXT: cmhi v3.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
+; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <8 x i8> @llvm.ucmp(<8 x i8> %a, <8 x i8> %b)
+ ret <8 x i8> %c
+}
+
+define <16 x i8> @u_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-SD-LABEL: u_v16i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.16b, #1
+; CHECK-SD-NEXT: cmhi v3.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: and v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v16i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.16b, #1
+; CHECK-GI-NEXT: cmhi v3.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <16 x i8> @llvm.ucmp(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %c
+}
+
+define <4 x i16> @u_v4i16(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-SD-LABEL: u_v4i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4h, #1
+; CHECK-SD-NEXT: cmhi v3.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: cmhi v0.4h, v1.4h, v0.4h
+; CHECK-SD-NEXT: and v1.8b, v3.8b, v2.8b
+; CHECK-SD-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v4i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4h, #1
+; CHECK-GI-NEXT: cmhi v3.4h, v0.4h, v1.4h
+; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
+; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <4 x i16> @llvm.ucmp(<4 x i16> %a, <4 x i16> %b)
+ ret <4 x i16> %c
+}
+
+define <8 x i16> @u_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-SD-LABEL: u_v8i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.8h, #1
+; CHECK-SD-NEXT: cmhi v3.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-SD-NEXT: and v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v8i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.8h, #1
+; CHECK-GI-NEXT: cmhi v3.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.8h, v1.8h, v0.8h
+; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <8 x i16> @llvm.ucmp(<8 x i16> %a, <8 x i16> %b)
+ ret <8 x i16> %c
+}
+
+define <16 x i16> @u_v16i16(<16 x i16> %a, <16 x i16> %b) {
+; CHECK-SD-LABEL: u_v16i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v4.8h, #1
+; CHECK-SD-NEXT: cmhi v5.8h, v0.8h, v2.8h
+; CHECK-SD-NEXT: cmhi v6.8h, v1.8h, v3.8h
+; CHECK-SD-NEXT: cmhi v0.8h, v2.8h, v0.8h
+; CHECK-SD-NEXT: cmhi v1.8h, v3.8h, v1.8h
+; CHECK-SD-NEXT: and v2.16b, v5.16b, v4.16b
+; CHECK-SD-NEXT: and v3.16b, v6.16b, v4.16b
+; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v16i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v4.8h, #1
+; CHECK-GI-NEXT: cmhi v5.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: cmhi v6.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.8h, v2.8h, v0.8h
+; CHECK-GI-NEXT: cmhi v1.8h, v3.8h, v1.8h
+; CHECK-GI-NEXT: and v5.16b, v4.16b, v5.16b
+; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b
+; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v5.16b
+; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v4.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <16 x i16> @llvm.ucmp(<16 x i16> %a, <16 x i16> %b)
+ ret <16 x i16> %c
+}
+
+define <2 x i32> @u_v2i32(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-SD-LABEL: u_v2i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2s, #1
+; CHECK-SD-NEXT: cmhi v3.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: cmhi v0.2s, v1.2s, v0.2s
+; CHECK-SD-NEXT: and v1.8b, v3.8b, v2.8b
+; CHECK-SD-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v2i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2s, #1
+; CHECK-GI-NEXT: cmhi v3.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: movi d4, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: and v2.8b, v2.8b, v3.8b
+; CHECK-GI-NEXT: bsl v0.8b, v4.8b, v2.8b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <2 x i32> @llvm.ucmp(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %c
+}
+
+define <4 x i32> @u_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-SD-LABEL: u_v4i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.4s, #1
+; CHECK-SD-NEXT: cmhi v3.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: and v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v4i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: cmhi v3.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <4 x i32> @llvm.ucmp(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %c
+}
+
+define <8 x i32> @u_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; CHECK-SD-LABEL: u_v8i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v4.4s, #1
+; CHECK-SD-NEXT: cmhi v5.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT: cmhi v6.4s, v1.4s, v3.4s
+; CHECK-SD-NEXT: cmhi v0.4s, v2.4s, v0.4s
+; CHECK-SD-NEXT: cmhi v1.4s, v3.4s, v1.4s
+; CHECK-SD-NEXT: and v2.16b, v5.16b, v4.16b
+; CHECK-SD-NEXT: and v3.16b, v6.16b, v4.16b
+; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v8i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v4.4s, #1
+; CHECK-GI-NEXT: cmhi v5.4s, v0.4s, v2.4s
+; CHECK-GI-NEXT: cmhi v6.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.4s, v2.4s, v0.4s
+; CHECK-GI-NEXT: cmhi v1.4s, v3.4s, v1.4s
+; CHECK-GI-NEXT: and v5.16b, v4.16b, v5.16b
+; CHECK-GI-NEXT: and v4.16b, v4.16b, v6.16b
+; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v5.16b
+; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v4.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <8 x i32> @llvm.ucmp(<8 x i32> %a, <8 x i32> %b)
+ ret <8 x i32> %c
+}
+
+define <2 x i64> @u_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-SD-LABEL: u_v2i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: cmhi v2.2d, v0.2d, v1.2d
+; CHECK-SD-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-SD-NEXT: dup v3.2d, x8
+; CHECK-SD-NEXT: and v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: orr v0.16b, v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v2i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI17_0
+; CHECK-GI-NEXT: cmhi v2.2d, v0.2d, v1.2d
+; CHECK-GI-NEXT: movi v4.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI17_0]
+; CHECK-GI-NEXT: cmhi v0.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: and v2.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <2 x i64> @llvm.ucmp(<2 x i64> %a, <2 x i64> %b)
+ ret <2 x i64> %c
+}
+
+define <4 x i64> @u_v4i64(<4 x i64> %a, <4 x i64> %b) {
+; CHECK-SD-LABEL: u_v4i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov w8, #1 // =0x1
+; CHECK-SD-NEXT: cmhi v4.2d, v0.2d, v2.2d
+; CHECK-SD-NEXT: cmhi v6.2d, v1.2d, v3.2d
+; CHECK-SD-NEXT: dup v5.2d, x8
+; CHECK-SD-NEXT: cmhi v0.2d, v2.2d, v0.2d
+; CHECK-SD-NEXT: cmhi v1.2d, v3.2d, v1.2d
+; CHECK-SD-NEXT: and v2.16b, v4.16b, v5.16b
+; CHECK-SD-NEXT: and v3.16b, v6.16b, v5.16b
+; CHECK-SD-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: orr v1.16b, v3.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: u_v4i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI18_0
+; CHECK-GI-NEXT: cmhi v4.2d, v0.2d, v2.2d
+; CHECK-GI-NEXT: cmhi v6.2d, v1.2d, v3.2d
+; CHECK-GI-NEXT: ldr q5, [x8, :lo12:.LCPI18_0]
+; CHECK-GI-NEXT: movi v7.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: cmhi v0.2d, v2.2d, v0.2d
+; CHECK-GI-NEXT: cmhi v1.2d, v3.2d, v1.2d
+; CHECK-GI-NEXT: and v4.16b, v5.16b, v4.16b
+; CHECK-GI-NEXT: and v5.16b, v5.16b, v6.16b
+; CHECK-GI-NEXT: bsl v0.16b, v7.16b, v4.16b
+; CHECK-GI-NEXT: bsl v1.16b, v7.16b, v5.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %c = call <4 x i64> @llvm.ucmp(<4 x i64> %a, <4 x i64> %b)
+ ret <4 x i64> %c
+}
+
+define <16 x i8> @signOf_neon(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_lo, <8 x i16> %s1_hi) {
+; CHECK-SD-LABEL: signOf_neon:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: cmhi v5.8h, v0.8h, v2.8h
+; CHECK-SD-NEXT: cmhi v2.8h, v2.8h, v0.8h
+; CHECK-SD-NEXT: cmhi v4.8h, v1.8h, v3.8h
+; CHECK-SD-NEXT: cmhi v1.8h, v3.8h, v1.8h
+; CHECK-SD-NEXT: umov w8, v5.h[1]
+; CHECK-SD-NEXT: umov w9, v2.h[1]
+; CHECK-SD-NEXT: umov w10, v5.h[0]
+; CHECK-SD-NEXT: umov w11, v2.h[0]
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst w9, #0xffff
+; CHECK-SD-NEXT: csinv w8, w8, wzr, eq
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v5.h[2]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w11, #0xffff
+; CHECK-SD-NEXT: umov w11, v2.h[2]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: fmov s0, w9
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[3]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w11, #0xffff
+; CHECK-SD-NEXT: mov v0.b[1], w8
+; CHECK-SD-NEXT: umov w8, v5.h[3]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[2], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v5.h[4]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[4]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[3], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v5.h[5]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[5]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[4], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v5.h[6]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[6]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[5], w9
+; CHECK-SD-NEXT: umov w9, v5.h[7]
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v2.h[7]
+; CHECK-SD-NEXT: csinv w8, w8, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[6], w8
+; CHECK-SD-NEXT: tst w9, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[0]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[0]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[7], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[1]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[1]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[8], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[2]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[2]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[9], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[3]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[3]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[10], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[4]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[4]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[11], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[5]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[5]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[12], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[6]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[6]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[13], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: umov w8, v4.h[7]
+; CHECK-SD-NEXT: cset w9, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: umov w10, v1.h[7]
+; CHECK-SD-NEXT: csinv w9, w9, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[14], w9
+; CHECK-SD-NEXT: tst w8, #0xffff
+; CHECK-SD-NEXT: cset w8, ne
+; CHECK-SD-NEXT: tst w10, #0xffff
+; CHECK-SD-NEXT: csinv w8, w8, wzr, eq
+; CHECK-SD-NEXT: mov v0.b[15], w8
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: signOf_neon:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: cmhi v4.8h, v0.8h, v2.8h
+; CHECK-GI-NEXT: cmhi v5.8h, v1.8h, v3.8h
+; CHECK-GI-NEXT: cmhi v0.8h, v2.8h, v0.8h
+; CHECK-GI-NEXT: cmhi v1.8h, v3.8h, v1.8h
+; CHECK-GI-NEXT: movi v2.16b, #1
+; CHECK-GI-NEXT: movi v3.2d, #0xffffffffffffffff
+; CHECK-GI-NEXT: uzp1 v4.16b, v4.16b, v5.16b
+; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: shl v1.16b, v4.16b, #7
+; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
+; CHECK-GI-NEXT: sshr v1.16b, v1.16b, #7
+; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
+; CHECK-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: bsl v0.16b, v3.16b, v1.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = shufflevector <8 x i16> %s0_lo, <8 x i16> %s0_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %1 = shufflevector <8 x i16> %s1_lo, <8 x i16> %s1_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+ %or.i = tail call <16 x i8> @llvm.ucmp.v16i8.v16i16(<16 x i16> %0, <16 x i16> %1)
+ ret <16 x i8> %or.i
+}
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