[llvm] [AArch64][CostModel] Reduce the cost of fadd reduction with fast flag (PR #108791)
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 16 03:04:15 PDT 2024
================
@@ -4147,6 +4147,22 @@ AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
switch (ISD) {
default:
break;
+ case ISD::FADD: {
+ if (MTy.isVector()) {
+ // FIXME: Consider cases where the number of vector elements is not power
+ // of 2.
+ const unsigned NElts = MTy.getVectorNumElements();
+ if (ValTy->getElementCount().getFixedValue() >= 2 && NElts >= 2 &&
----------------
david-arm wrote:
I'm not sure if this is right. What about scalable vectors? Do we lower to faddp using SVE as well?
https://github.com/llvm/llvm-project/pull/108791
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