[llvm] [RISCV] Custom legalize f16/bf16 FNEG/FABS with Zfhmin/Zbfmin. (PR #106886)

[Craig Topper via llvm-commits]

topperc wrote:

> LG. BTW we have the same problem with f16/bf16 fcopysign.
> 
> ```
> 
> ; bin/llc -mtriple=riscv64 -mattr=+zfhmin test.ll -o -
> 
> define half @test(half %a, half %b) nounwind {
> 
>   %t = call half @llvm.copysign.f16(half %a, half %b)
> 
>   ret half %t
> 
> }
> 
> ```
> 
> ```
> 
>         addi    sp, sp, -16
> 
>         fsh     fa1, 8(sp)
> 
>         fsh     fa0, 0(sp)
> 
>         lbu     a0, 9(sp)
> 
>         lbu     a1, 1(sp)
> 
>         andi    a0, a0, 128
> 
>         andi    a1, a1, 127
> 
>         or      a0, a1, a0
> 
>         sb      a0, 1(sp)
> 
>         flh     fa0, 0(sp)
> 
>         addi    sp, sp, 16
> 
>         ret
> 
> ```

I know. It needs a more complex fix because of the two operands and the sign operand can be a different type. I'll work on it soon.

We should also stop promoting ISD::SELECT.

https://github.com/llvm/llvm-project/pull/106886