[llvm] [CodeGen] Update a few places that were passing Register to raw_ostream::operator<< (PR #106877)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 31 15:27:33 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/106877
These would implicitly cast the register to `unsigned`. Switch most of them to use printReg will give a more readable output. Change some others to use Register::id() so we can eventually remove the implicit cast to `unsigned`.
>From 6a1372cf7720c1841dabba84e0aaa327ed2ce80e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 31 Aug 2024 15:24:06 -0700
Subject: [PATCH] [CodeGen] Update a few places that were passing Register to
raw_ostream::operator<<
These would implicitly cast the register to `unsigned`. Switch
most of them to use printReg will give a more readable output.
---
llvm/lib/CodeGen/InitUndef.cpp | 2 +-
llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp | 4 ++--
llvm/lib/CodeGen/LiveDebugVariables.cpp | 10 ++++------
llvm/lib/CodeGen/LocalStackSlotAllocation.cpp | 3 ++-
llvm/lib/CodeGen/TargetRegisterInfo.cpp | 2 +-
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 5 +++--
llvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp | 2 +-
.../lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp | 7 ++++---
8 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/CodeGen/InitUndef.cpp b/llvm/lib/CodeGen/InitUndef.cpp
index 51c50ff872ef21..7c1b90afd495e7 100644
--- a/llvm/lib/CodeGen/InitUndef.cpp
+++ b/llvm/lib/CodeGen/InitUndef.cpp
@@ -198,7 +198,7 @@ bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
LLVM_DEBUG(
dbgs() << "Emitting PseudoInitUndef Instruction for implicit register "
- << MO.getReg() << '\n');
+ << printReg(MO.getReg()) << '\n');
const TargetRegisterClass *TargetRegClass =
TRI->getLargestSuperClass(MRI->getRegClass(MO.getReg()));
diff --git a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
index 2959d3261bea71..2d95ff9e05abe7 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/VarLocBasedImpl.cpp
@@ -1789,14 +1789,14 @@ void VarLocBasedLDV::transferSpillOrRestoreInst(MachineInstr &MI,
if (isLocationSpill(MI, MF, Reg)) {
TKind = TransferKind::TransferSpill;
LLVM_DEBUG(dbgs() << "Recognized as spill: "; MI.dump(););
- LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
+ LLVM_DEBUG(dbgs() << "Register: " << Reg.id() << " " << printReg(Reg, TRI)
<< "\n");
} else {
if (!(Loc = isRestoreInstruction(MI, MF, Reg)))
return;
TKind = TransferKind::TransferRestore;
LLVM_DEBUG(dbgs() << "Recognized as restore: "; MI.dump(););
- LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
+ LLVM_DEBUG(dbgs() << "Register: " << Reg.id() << " " << printReg(Reg, TRI)
<< "\n");
}
// Check if the register or spill location is the location of a debug value.
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index 48bcc0a61e30c9..822a1beb489592 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -1873,12 +1873,10 @@ void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
Builder.addImm(regSizeInBits);
}
- LLVM_DEBUG(
- if (SpillOffset != 0) {
- dbgs() << "DBG_PHI for Vreg " << Reg << " subreg " << SubReg <<
- " has nonzero offset\n";
- }
- );
+ LLVM_DEBUG(if (SpillOffset != 0) {
+ dbgs() << "DBG_PHI for " << printReg(Reg, TRI, SubReg)
+ << " has nonzero offset\n";
+ });
}
// If there was no mapping for a value ID, it's optimized out. Create no
// DBG_PHI, and any variables using this value will become optimized out.
diff --git a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
index 0bb7953efd52f4..0e9f041f7bfdfe 100644
--- a/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
+++ b/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
@@ -407,7 +407,8 @@ bool LocalStackSlotImpl::insertFrameReferenceRegisters(MachineFunction &Fn) {
if (BaseReg.isValid() &&
lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust,
LocalOffset, MI, TRI)) {
- LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
+ LLVM_DEBUG(dbgs() << " Reusing base register " << printReg(BaseReg)
+ << "\n");
// We found a register to reuse.
Offset = FrameSizeAdjust + LocalOffset - BaseOffset;
} else {
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 16dab974efacb2..ac9a3d6f0d1a60 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -120,7 +120,7 @@ Printable printReg(Register Reg, const TargetRegisterInfo *TRI,
OS << '%' << Register::virtReg2Index(Reg);
}
} else if (!TRI)
- OS << '$' << "physreg" << Reg;
+ OS << '$' << "physreg" << Reg.id();
else if (Reg < TRI->getNumRegs()) {
OS << '$';
printLowerCase(TRI->getName(Reg), OS);
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index ddce80b2ae129e..296ff0dfb75bd5 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -2182,8 +2182,9 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
return false;
}
- LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", "
- << MAddr.Base.LoReg << "} Offset: " << MAddr.Offset << "\n\n";);
+ LLVM_DEBUG(dbgs() << " BASE: {" << printReg(MAddr.Base.HiReg, TRI) << ", "
+ << printReg(MAddr.Base.LoReg, TRI)
+ << "} Offset: " << MAddr.Offset << "\n\n";);
// Step2: Traverse through MI's basic block and find an anchor(that has the
// same base-registers) with the highest 13bit distance from MI's offset.
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp
index 4a75bab6b95ddc..283d93408575b5 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyDebugFixup.cpp
@@ -107,7 +107,7 @@ bool WebAssemblyDebugFixup::runOnMachineFunction(MachineFunction &MF) {
for (auto &Elem : reverse(Stack)) {
if (MO.getReg() == Elem.Reg) {
auto Depth = static_cast<unsigned>(&Elem - &Stack[0]);
- LLVM_DEBUG(dbgs() << "Debug Value VReg " << MO.getReg()
+ LLVM_DEBUG(dbgs() << "Debug Value VReg " << printReg(MO.getReg())
<< " -> Stack Relative " << Depth << "\n");
MO.ChangeToTargetIndex(WebAssembly::TI_OPERAND_STACK, Depth);
// Save the DBG_VALUE instruction that defined this stackified
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp
index 1203b343bf24bf..3dc9cdc11eb575 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp
@@ -76,7 +76,7 @@ bool WebAssemblyRegNumbering::runOnMachineFunction(MachineFunction &MF) {
break;
int64_t Imm = MI.getOperand(1).getImm();
- LLVM_DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg()
+ LLVM_DEBUG(dbgs() << "Arg VReg " << printReg(MI.getOperand(0).getReg())
<< " -> WAReg " << Imm << "\n");
MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
}
@@ -95,13 +95,14 @@ bool WebAssemblyRegNumbering::runOnMachineFunction(MachineFunction &MF) {
continue;
// Handle stackified registers.
if (MFI.isVRegStackified(VReg)) {
- LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg "
+ LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg "
<< (INT32_MIN | NumStackRegs) << "\n");
MFI.setWAReg(VReg, INT32_MIN | NumStackRegs++);
continue;
}
if (MFI.getWAReg(VReg) == WebAssembly::UnusedReg) {
- LLVM_DEBUG(dbgs() << "VReg " << VReg << " -> WAReg " << CurReg << "\n");
+ LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg " << CurReg
+ << "\n");
MFI.setWAReg(VReg, CurReg++);
}
}
More information about the llvm-commits
mailing list