[llvm] 6d9c6f0 - [RISCV] Use MCRegister for return value from allocateRVVReg. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-08-31T10:30:44-07:00
New Revision: 6d9c6f0ca5957f112b790be479b52ed86950ef12

URL: https://github.com/llvm/llvm-project/commit/6d9c6f0ca5957f112b790be479b52ed86950ef12
DIFF: https://github.com/llvm/llvm-project/commit/6d9c6f0ca5957f112b790be479b52ed86950ef12.diff

LOG: [RISCV] Use MCRegister for return value from allocateRVVReg. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ebe3ac8620c8e5..1b0befb1d70738 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18976,9 +18976,10 @@ static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1,
   return false;
 }
 
-static unsigned allocateRVVReg(MVT ValVT, unsigned ValNo,
-                               std::optional<unsigned> FirstMaskArgument,
-                               CCState &State, const RISCVTargetLowering &TLI) {
+static MCRegister allocateRVVReg(MVT ValVT, unsigned ValNo,
+                                 std::optional<unsigned> FirstMaskArgument,
+                                 CCState &State,
+                                 const RISCVTargetLowering &TLI) {
   const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT);
   if (RC == &RISCV::VRRegClass) {
     // Assign the first mask argument to V0.