[llvm] 8c5d53f - [RISCV] Use MCRegister instead of unsigned in RISCVAsmParser.cpp. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 31 01:03:08 PDT 2024
Author: Craig Topper
Date: 2024-08-31T01:02:50-07:00
New Revision: 8c5d53f8deb26456432cc0459551cdd69754fea7
URL: https://github.com/llvm/llvm-project/commit/8c5d53f8deb26456432cc0459551cdd69754fea7
DIFF: https://github.com/llvm/llvm-project/commit/8c5d53f8deb26456432cc0459551cdd69754fea7.diff
LOG: [RISCV] Use MCRegister instead of unsigned in RISCVAsmParser.cpp. NFC
Rename RegNo to Reg.
Added:
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index f299e823aa3f50..6d33a1f64195d5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1110,9 +1110,9 @@ struct RISCVOperand final : public MCParsedAsmOperand {
}
static std::unique_ptr<RISCVOperand>
- createReg(unsigned RegNo, SMLoc S, SMLoc E, bool IsGPRAsFPR = false) {
+ createReg(MCRegister Reg, SMLoc S, SMLoc E, bool IsGPRAsFPR = false) {
auto Op = std::make_unique<RISCVOperand>(KindTy::Register);
- Op->Reg.RegNum = RegNo;
+ Op->Reg.RegNum = Reg.id();
Op->Reg.IsGPRAsFPR = IsGPRAsFPR;
Op->StartLoc = S;
Op->EndLoc = E;
@@ -1181,11 +1181,11 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return Op;
}
- static std::unique_ptr<RISCVOperand> createRegReg(unsigned Reg1No,
- unsigned Reg2No, SMLoc S) {
+ static std::unique_ptr<RISCVOperand> createRegReg(MCRegister Reg1,
+ MCRegister Reg2, SMLoc S) {
auto Op = std::make_unique<RISCVOperand>(KindTy::RegReg);
- Op->RegReg.Reg1 = Reg1No;
- Op->RegReg.Reg2 = Reg2No;
+ Op->RegReg.Reg1 = Reg1.id();
+ Op->RegReg.Reg2 = Reg2.id();
Op->StartLoc = S;
Op->EndLoc = S;
return Op;
@@ -1310,7 +1310,7 @@ static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
else if (Kind == MCK_VRM8)
RegClassID = RISCV::VRM8RegClassID;
else
- return 0;
+ return MCRegister();
return RI.getMatchingSuperReg(Reg, RISCV::sub_vrm1_0,
&RISCVMCRegisterClasses[RegClassID]);
}
@@ -1661,9 +1661,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
}
// Attempts to match Name as a register (either using the default name or
-// alternative ABI names), setting RegNo to the matching register. Upon
-// failure, returns a non-valid MCRegister. If IsRVE, then registers x16-x31
-// will be rejected.
+// alternative ABI names), returning the matching register. Upon failure,
+// returns a non-valid MCRegister. If IsRVE, then registers x16-x31 will be
+// rejected.
MCRegister RISCVAsmParser::matchRegisterNameHelper(StringRef Name) const {
MCRegister Reg = MatchRegisterName(Name);
// The 16-/32- and 64-bit FPRs have the same asm name. Check that the initial
@@ -1676,7 +1676,7 @@ MCRegister RISCVAsmParser::matchRegisterNameHelper(StringRef Name) const {
if (!Reg)
Reg = MatchRegisterAltName(Name);
if (isRVE() && Reg >= RISCV::X16 && Reg <= RISCV::X31)
- Reg = RISCV::NoRegister;
+ Reg = MCRegister();
return Reg;
}
@@ -1727,9 +1727,9 @@ ParseStatus RISCVAsmParser::parseRegister(OperandVector &Operands,
return ParseStatus::NoMatch;
case AsmToken::Identifier:
StringRef Name = getLexer().getTok().getIdentifier();
- MCRegister RegNo = matchRegisterNameHelper(Name);
+ MCRegister Reg = matchRegisterNameHelper(Name);
- if (!RegNo) {
+ if (!Reg) {
if (HadParens)
getLexer().UnLex(LParen);
return ParseStatus::NoMatch;
@@ -1739,7 +1739,7 @@ ParseStatus RISCVAsmParser::parseRegister(OperandVector &Operands,
SMLoc S = getLoc();
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
getLexer().Lex();
- Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
+ Operands.push_back(RISCVOperand::createReg(Reg, S, E));
}
if (HadParens) {
@@ -2305,16 +2305,16 @@ ParseStatus RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
StringRef Name = getLexer().getTok().getIdentifier();
if (!Name.consume_back(".t"))
return Error(getLoc(), "expected '.t' suffix");
- MCRegister RegNo = matchRegisterNameHelper(Name);
+ MCRegister Reg = matchRegisterNameHelper(Name);
- if (!RegNo)
+ if (!Reg)
return ParseStatus::NoMatch;
- if (RegNo != RISCV::V0)
+ if (Reg != RISCV::V0)
return ParseStatus::NoMatch;
SMLoc S = getLoc();
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
getLexer().Lex();
- Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
+ Operands.push_back(RISCVOperand::createReg(Reg, S, E));
return ParseStatus::Success;
}
@@ -2323,15 +2323,15 @@ ParseStatus RISCVAsmParser::parseGPRAsFPR(OperandVector &Operands) {
return ParseStatus::NoMatch;
StringRef Name = getLexer().getTok().getIdentifier();
- MCRegister RegNo = matchRegisterNameHelper(Name);
+ MCRegister Reg = matchRegisterNameHelper(Name);
- if (!RegNo)
+ if (!Reg)
return ParseStatus::NoMatch;
SMLoc S = getLoc();
SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
getLexer().Lex();
Operands.push_back(RISCVOperand::createReg(
- RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
+ Reg, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
return ParseStatus::Success;
}
@@ -2354,15 +2354,15 @@ ParseStatus RISCVAsmParser::parseGPRPair(OperandVector &Operands,
return ParseStatus::NoMatch;
StringRef Name = getLexer().getTok().getIdentifier();
- MCRegister RegNo = matchRegisterNameHelper(Name);
+ MCRegister Reg = matchRegisterNameHelper(Name);
- if (!RegNo)
+ if (!Reg)
return ParseStatus::NoMatch;
- if (!RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(RegNo))
+ if (!RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg))
return ParseStatus::NoMatch;
- if ((RegNo - RISCV::X0) & 1)
+ if ((Reg - RISCV::X0) & 1)
return TokError("register must be even");
SMLoc S = getLoc();
@@ -2370,8 +2370,8 @@ ParseStatus RISCVAsmParser::parseGPRPair(OperandVector &Operands,
getLexer().Lex();
const MCRegisterInfo *RI = getContext().getRegisterInfo();
- unsigned Pair = RI->getMatchingSuperReg(
- RegNo, RISCV::sub_gpr_even,
+ MCRegister Pair = RI->getMatchingSuperReg(
+ Reg, RISCV::sub_gpr_even,
&RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
Operands.push_back(RISCVOperand::createReg(Pair, S, E));
return ParseStatus::Success;
@@ -2629,7 +2629,7 @@ ParseStatus RISCVAsmParser::parseReglist(OperandVector &Operands) {
if (getLexer().isNot(AsmToken::Identifier))
return Error(getLoc(), "invalid register");
EndName = getLexer().getTok().getIdentifier();
- if (MatchRegisterName(EndName) == RISCV::NoRegister)
+ if (!MatchRegisterName(EndName))
return Error(getLoc(), "invalid register");
getLexer().Lex();
}
@@ -2644,7 +2644,7 @@ ParseStatus RISCVAsmParser::parseReglist(OperandVector &Operands) {
if (parseToken(AsmToken::RCurly, "register list must end with '}'"))
return ParseStatus::Failure;
- if (RegEnd == RISCV::NoRegister)
+ if (!RegEnd)
RegEnd = RegStart;
auto Encode = RISCVZC::encodeRlist(RegEnd, IsEABI);
@@ -3356,7 +3356,7 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
.addOperand(Inst.getOperand(0))
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
- .addReg(RISCV::NoRegister)
+ .addReg(MCRegister())
.setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMNAND_MM)
.addOperand(Inst.getOperand(0))
@@ -3395,7 +3395,7 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
.addOperand(Inst.getOperand(3))
- .addReg(RISCV::NoRegister)
+ .addReg(MCRegister())
.setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
.addOperand(Inst.getOperand(0))
@@ -3414,7 +3414,7 @@ void RISCVAsmParser::emitVMSGE(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
.addOperand(Inst.getOperand(1))
.addOperand(Inst.getOperand(2))
.addOperand(Inst.getOperand(3))
- .addReg(RISCV::NoRegister)
+ .addReg(MCRegister())
.setLoc(IDLoc));
emitToStreamer(Out, MCInstBuilder(RISCV::VMANDN_MM)
.addOperand(Inst.getOperand(1))
@@ -3461,8 +3461,7 @@ bool RISCVAsmParser::checkPseudoTLSDESCCall(MCInst &Inst,
}
std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultMaskRegOp() const {
- return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(),
- llvm::SMLoc());
+ return RISCVOperand::createReg(MCRegister(), llvm::SMLoc(), llvm::SMLoc());
}
std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultFRMArgOp() const {
@@ -3481,8 +3480,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
if (Opcode == RISCV::PseudoVMSGEU_VX_M_T ||
Opcode == RISCV::PseudoVMSGE_VX_M_T) {
- unsigned DestReg = Inst.getOperand(0).getReg();
- unsigned TempReg = Inst.getOperand(1).getReg();
+ MCRegister DestReg = Inst.getOperand(0).getReg();
+ MCRegister TempReg = Inst.getOperand(1).getReg();
if (DestReg == TempReg) {
SMLoc Loc = Operands.back()->getStartLoc();
return Error(Loc, "the temporary vector register cannot be the same as "
@@ -3492,9 +3491,9 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
if (Opcode == RISCV::TH_LDD || Opcode == RISCV::TH_LWUD ||
Opcode == RISCV::TH_LWD) {
- unsigned Rd1 = Inst.getOperand(0).getReg();
- unsigned Rd2 = Inst.getOperand(1).getReg();
- unsigned Rs1 = Inst.getOperand(2).getReg();
+ MCRegister Rd1 = Inst.getOperand(0).getReg();
+ MCRegister Rd2 = Inst.getOperand(1).getReg();
+ MCRegister Rs1 = Inst.getOperand(2).getReg();
// The encoding with rd1 == rd2 == rs1 is reserved for XTHead load pair.
if (Rs1 == Rd1 && Rs1 == Rd2) {
SMLoc Loc = Operands[1]->getStartLoc();
@@ -3503,8 +3502,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
}
if (Opcode == RISCV::CM_MVSA01) {
- unsigned Rd1 = Inst.getOperand(0).getReg();
- unsigned Rd2 = Inst.getOperand(1).getReg();
+ MCRegister Rd1 = Inst.getOperand(0).getReg();
+ MCRegister Rd2 = Inst.getOperand(1).getReg();
if (Rd1 == Rd2) {
SMLoc Loc = Operands[1]->getStartLoc();
return Error(Loc, "rs1 and rs2 must be
diff erent");
@@ -3531,16 +3530,16 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
if (Opcode == RISCV::VC_V_XVW || Opcode == RISCV::VC_V_IVW ||
Opcode == RISCV::VC_V_FVW || Opcode == RISCV::VC_V_VVW) {
// Operands Opcode, Dst, uimm, Dst, Rs2, Rs1 for VC_V_XVW.
- unsigned VCIXDst = Inst.getOperand(0).getReg();
+ MCRegister VCIXDst = Inst.getOperand(0).getReg();
SMLoc VCIXDstLoc = Operands[2]->getStartLoc();
if (MCID.TSFlags & RISCVII::VS1Constraint) {
- unsigned VCIXRs1 = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
+ MCRegister VCIXRs1 = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
if (VCIXDst == VCIXRs1)
return Error(VCIXDstLoc, "the destination vector register group cannot"
" overlap the source vector register group");
}
if (MCID.TSFlags & RISCVII::VS2Constraint) {
- unsigned VCIXRs2 = Inst.getOperand(Inst.getNumOperands() - 2).getReg();
+ MCRegister VCIXRs2 = Inst.getOperand(Inst.getNumOperands() - 2).getReg();
if (VCIXDst == VCIXRs2)
return Error(VCIXDstLoc, "the destination vector register group cannot"
" overlap the source vector register group");
@@ -3548,7 +3547,7 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
return false;
}
- unsigned DestReg = Inst.getOperand(0).getReg();
+ MCRegister DestReg = Inst.getOperand(0).getReg();
unsigned Offset = 0;
int TiedOp = MCID.getOperandConstraint(1, MCOI::TIED_TO);
if (TiedOp == 0)
@@ -3557,13 +3556,13 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
// Operands[1] will be the first operand, DestReg.
SMLoc Loc = Operands[1]->getStartLoc();
if (MCID.TSFlags & RISCVII::VS2Constraint) {
- unsigned CheckReg = Inst.getOperand(Offset + 1).getReg();
+ MCRegister CheckReg = Inst.getOperand(Offset + 1).getReg();
if (DestReg == CheckReg)
return Error(Loc, "the destination vector register group cannot overlap"
" the source vector register group");
}
if ((MCID.TSFlags & RISCVII::VS1Constraint) && Inst.getOperand(Offset + 2).isReg()) {
- unsigned CheckReg = Inst.getOperand(Offset + 2).getReg();
+ MCRegister CheckReg = Inst.getOperand(Offset + 2).getReg();
if (DestReg == CheckReg)
return Error(Loc, "the destination vector register group cannot overlap"
" the source vector register group");
@@ -3582,8 +3581,8 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
// same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
// actually. We need to check the last operand to ensure whether it is
// masked or not.
- unsigned CheckReg = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
- assert((CheckReg == RISCV::V0 || CheckReg == RISCV::NoRegister) &&
+ MCRegister CheckReg = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
+ assert((CheckReg == RISCV::V0 || !CheckReg) &&
"Unexpected register for mask operand");
if (DestReg == CheckReg)
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