[llvm] e6e4291 - [RISCV] Cleanup CHECK prefixes in half-arith.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 30 18:58:00 PDT 2024
Author: Craig Topper
Date: 2024-08-30T18:57:50-07:00
New Revision: e6e429179ecd425040af2bd475f090b503b047c9
URL: https://github.com/llvm/llvm-project/commit/e6e429179ecd425040af2bd475f090b503b047c9
DIFF: https://github.com/llvm/llvm-project/commit/e6e429179ecd425040af2bd475f090b503b047c9.diff
LOG: [RISCV] Cleanup CHECK prefixes in half-arith.ll. NFC
Remove prefixes that donn't appear on RUN lines.
Rename prefixes for consistency.
Add RV32/RV64 prefixes where necessary to fix a conflict.
Added:
Modified:
llvm/test/CodeGen/RISCV/half-arith.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
index 59981a282ab43e..f00829530bb97e 100644
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -4,21 +4,21 @@
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
-; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECK-ZHINX %s
+; RUN: -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
-; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECK-ZHINX %s
+; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,CHECK-RV32-FSGNJ %s
+; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck --check-prefixes=CHECKIZFHMIN,CHECK-RV64-FSGNJ %s
+; RUN: -target-abi lp64f < %s | FileCheck --check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
-; RUN: -target-abi ilp32 < %s | FileCheck --check-prefixes=CHECKZHINXMIN %s
+; RUN: -target-abi ilp32 < %s | FileCheck --check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
-; RUN: -target-abi lp64 < %s | FileCheck --check-prefixes=CHECKZHINXMIN %s
+; RUN: -target-abi lp64 < %s | FileCheck --check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
; These tests are each targeted at a particular RISC-V FPU instruction.
; Compares and conversions can be found in half-fcmp.ll and half-convert.ll
@@ -31,10 +31,10 @@ define half @fadd_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fadd_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fadd_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fadd_s:
; RV32I: # %bb.0:
@@ -96,20 +96,13 @@ define half @fadd_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fadd_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fadd.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fadd_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fadd_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = fadd half %a, %b
ret half %1
}
@@ -120,10 +113,10 @@ define half @fsub_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fsub.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fsub_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fsub.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fsub_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fsub.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fsub_s:
; RV32I: # %bb.0:
@@ -185,20 +178,13 @@ define half @fsub_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fsub_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fsub.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fsub_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fsub.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fsub_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fsub.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = fsub half %a, %b
ret half %1
}
@@ -209,10 +195,10 @@ define half @fmul_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fmul.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fmul_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fmul.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fmul_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmul.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fmul_s:
; RV32I: # %bb.0:
@@ -274,20 +260,13 @@ define half @fmul_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fmul_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fmul_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fmul_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmul.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = fmul half %a, %b
ret half %1
}
@@ -298,10 +277,10 @@ define half @fdiv_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fdiv.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fdiv_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fdiv.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fdiv_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fdiv.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fdiv_s:
; RV32I: # %bb.0:
@@ -363,20 +342,13 @@ define half @fdiv_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fdiv_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fdiv.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fdiv_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fdiv.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fdiv_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fdiv.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = fdiv half %a, %b
ret half %1
}
@@ -389,10 +361,10 @@ define half @fsqrt_s(half %a) nounwind {
; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fsqrt_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fsqrt.h a0, a0
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fsqrt_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fsqrt.h a0, a0
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fsqrt_s:
; RV32I: # %bb.0:
@@ -427,18 +399,12 @@ define half @fsqrt_s(half %a) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fsqrt_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fsqrt.s a0, a0
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fsqrt_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fsqrt.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fsqrt_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fsqrt.s a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.sqrt.f16(half %a)
ret half %1
}
@@ -451,10 +417,10 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fsgnj_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fsgnj.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fsgnj_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fsgnj.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fsgnj_s:
; RV32I: # %bb.0:
@@ -474,79 +440,65 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fsgnj_s:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fsh fa1, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fsh fa0, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a1, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: andi a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: andi a1, a1, 127
-; CHECK-RV32-FSGNJ-NEXT: or a0, a1, a0
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa0, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fsgnj_s:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fsh fa1, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fsh fa0, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a1, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: andi a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: andi a1, a1, 127
-; CHECK-RV64-FSGNJ-NEXT: or a0, a1, a0
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa0, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fsgnj_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK-ZHINXMIN-NEXT: addi a2, sp, 12
-; CHECK-ZHINXMIN-NEXT: sh a1, 0(a2)
-; CHECK-ZHINXMIN-NEXT: addi a1, sp, 8
-; CHECK-ZHINXMIN-NEXT: sh a0, 0(a1)
-; CHECK-ZHINXMIN-NEXT: lbu a0, 13(sp)
-; CHECK-ZHINXMIN-NEXT: lbu a2, 9(sp)
-; CHECK-ZHINXMIN-NEXT: andi a0, a0, 128
-; CHECK-ZHINXMIN-NEXT: andi a2, a2, 127
-; CHECK-ZHINXMIN-NEXT: or a0, a2, a0
-; CHECK-ZHINXMIN-NEXT: sb a0, 9(sp)
-; CHECK-ZHINXMIN-NEXT: lh a0, 0(a1)
-; CHECK-ZHINXMIN-NEXT: addi sp, sp, 16
-; CHECK-ZHINXMIN-NEXT: ret
-; CHECKFSGNJ-LABEL: fsgnj_s:
-; CHECKFSGNJ: # %bb.0:
-; CHECKFSGNJ-NEXT: addi sp, sp, -16
-; CHECKFSGNJ-NEXT: fsh fa1, 12(sp)
-; CHECKFSGNJ-NEXT: fsh fa0, 8(sp)
-; CHECKFSGNJ-NEXT: lbu a0, 13(sp)
-; CHECKFSGNJ-NEXT: lbu a1, 9(sp)
-; CHECKFSGNJ-NEXT: andi a0, a0, 128
-; CHECKFSGNJ-NEXT: andi a1, a1, 127
-; CHECKFSGNJ-NEXT: or a0, a1, a0
-; CHECKFSGNJ-NEXT: sb a0, 9(sp)
-; CHECKFSGNJ-NEXT: flh fa0, 8(sp)
-; CHECKFSGNJ-NEXT: addi sp, sp, 16
-; CHECKFSGNJ-NEXT: ret
-; CHECK64FSGNJ-LABEL: fsgnj_s:
-; CHECK64FSGNJ: # %bb.0:
-; CHECK64FSGNJ-NEXT: addi sp, sp, -16
-; CHECK64FSGNJ-NEXT: fsh fa1, 8(sp)
-; CHECK64FSGNJ-NEXT: fsh fa0, 0(sp)
-; CHECK64FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK64FSGNJ-NEXT: lbu a1, 1(sp)
-; CHECK64FSGNJ-NEXT: andi a0, a0, 128
-; CHECK64FSGNJ-NEXT: andi a1, a1, 127
-; CHECK64FSGNJ-NEXT: or a0, a1, a0
-; CHECK64FSGNJ-NEXT: sb a0, 1(sp)
-; CHECK64FSGNJ-NEXT: flh fa0, 0(sp)
-; CHECK64FSGNJ-NEXT: addi sp, sp, 16
-; CHECK64FSGNJ-NEXT: ret
+; RV32IZFHMIN-LABEL: fsgnj_s:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fsh fa1, 12(sp)
+; RV32IZFHMIN-NEXT: fsh fa0, 8(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: lbu a1, 9(sp)
+; RV32IZFHMIN-NEXT: andi a0, a0, 128
+; RV32IZFHMIN-NEXT: andi a1, a1, 127
+; RV32IZFHMIN-NEXT: or a0, a1, a0
+; RV32IZFHMIN-NEXT: sb a0, 9(sp)
+; RV32IZFHMIN-NEXT: flh fa0, 8(sp)
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fsgnj_s:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fsh fa1, 8(sp)
+; RV64IZFHMIN-NEXT: fsh fa0, 0(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: lbu a1, 1(sp)
+; RV64IZFHMIN-NEXT: andi a0, a0, 128
+; RV64IZFHMIN-NEXT: andi a1, a1, 127
+; RV64IZFHMIN-NEXT: or a0, a1, a0
+; RV64IZFHMIN-NEXT: sb a0, 1(sp)
+; RV64IZFHMIN-NEXT: flh fa0, 0(sp)
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fsgnj_s:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: sh a1, 12(sp)
+; RV32IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: lbu a0, 13(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 9(sp)
+; RV32IZHINXMIN-NEXT: andi a0, a0, 128
+; RV32IZHINXMIN-NEXT: andi a1, a1, 127
+; RV32IZHINXMIN-NEXT: or a0, a1, a0
+; RV32IZHINXMIN-NEXT: sb a0, 9(sp)
+; RV32IZHINXMIN-NEXT: lh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fsgnj_s:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: sh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: sh a0, 0(sp)
+; RV64IZHINXMIN-NEXT: lbu a0, 9(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 1(sp)
+; RV64IZHINXMIN-NEXT: andi a0, a0, 128
+; RV64IZHINXMIN-NEXT: andi a1, a1, 127
+; RV64IZHINXMIN-NEXT: or a0, a1, a0
+; RV64IZHINXMIN-NEXT: sb a0, 1(sp)
+; RV64IZHINXMIN-NEXT: lh a0, 0(sp)
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%1 = call half @llvm.copysign.f16(half %a, half %b)
ret half %1
}
@@ -561,12 +513,12 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: feq.h a0, fa5, fa4
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fneg_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a0, a0, a0
-; CHECK-ZHINX-NEXT: fneg.h a1, a0
-; CHECK-ZHINX-NEXT: feq.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fneg_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a0, a0, a0
+; CHECKIZHINX-NEXT: fneg.h a1, a0
+; CHECKIZHINX-NEXT: feq.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fneg_s:
; RV32I: # %bb.0:
@@ -630,50 +582,73 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fneg_s:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa4, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV32-FSGNJ-NEXT: feq.s a0, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fneg_s:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa4, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV64-FSGNJ-NEXT: feq.s a0, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fneg_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fneg.s a1, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: feq.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fneg_s:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa4, 12(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV32IZFHMIN-NEXT: feq.s a0, fa5, fa4
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fneg_s:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa4, 8(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV64IZFHMIN-NEXT: feq.s a0, fa5, fa4
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fneg_s:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: sh a0, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 13(sp)
+; RV32IZHINXMIN-NEXT: xori a1, a1, 128
+; RV32IZHINXMIN-NEXT: sb a1, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a1, 12(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: feq.s a0, a0, a1
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fneg_s:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 9(sp)
+; RV64IZHINXMIN-NEXT: xori a1, a1, 128
+; RV64IZHINXMIN-NEXT: sb a1, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: feq.s a0, a0, a1
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%1 = fadd half %a, %a
%2 = fneg half %1
%3 = fcmp oeq half %1, %2
@@ -690,11 +665,11 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fsgnjn.h fa0, fa0, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fsgnjn_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a1, a0, a1
-; CHECK-ZHINX-NEXT: fsgnjn.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fsgnjn_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a1, a0, a1
+; CHECKIZHINX-NEXT: fsgnjn.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fsgnjn_s:
; RV32I: # %bb.0:
@@ -774,118 +749,101 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fsgnjn_s:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa0
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 4(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 5(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 5(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, 4(sp)
-; CHECK-RV32-FSGNJ-NEXT: fsh fa0, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a1, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: andi a0, a0, 127
-; CHECK-RV32-FSGNJ-NEXT: andi a1, a1, 128
-; CHECK-RV32-FSGNJ-NEXT: or a0, a0, a1
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa0, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fsgnjn_s:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -32
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa0
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fsh fa0, 16(sp)
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 24(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 17(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a1, 25(sp)
-; CHECK-RV64-FSGNJ-NEXT: andi a0, a0, 127
-; CHECK-RV64-FSGNJ-NEXT: andi a1, a1, 128
-; CHECK-RV64-FSGNJ-NEXT: or a0, a0, a1
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 17(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa0, 16(sp)
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 32
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fsgnjn_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: addi sp, sp, -16
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a1, a2, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fneg.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: addi a2, sp, 8
-; CHECK-ZHINXMIN-NEXT: sh a0, 0(a2)
-; CHECK-ZHINXMIN-NEXT: addi a0, sp, 12
-; CHECK-ZHINXMIN-NEXT: sh a1, 0(a0)
-; CHECK-ZHINXMIN-NEXT: lbu a0, 9(sp)
-; CHECK-ZHINXMIN-NEXT: lbu a1, 13(sp)
-; CHECK-ZHINXMIN-NEXT: andi a0, a0, 127
-; CHECK-ZHINXMIN-NEXT: andi a1, a1, 128
-; CHECK-ZHINXMIN-NEXT: or a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: sb a0, 9(sp)
-; CHECK-ZHINXMIN-NEXT: lh a0, 0(a2)
-; CHECK-ZHINXMIN-NEXT: addi sp, sp, 16
-; CHECK-ZHINXMIN-NEXT: ret
-; CHECKFSGNJ-LABEL: fsgnjn_s:
-; CHECKFSGNJ: # %bb.0:
-; CHECKFSGNJ-NEXT: addi sp, sp, -16
-; CHECKFSGNJ-NEXT: fcvt.s.h ft0, fa1
-; CHECKFSGNJ-NEXT: fcvt.s.h ft1, fa0
-; CHECKFSGNJ-NEXT: fadd.s ft0, ft1, ft0
-; CHECKFSGNJ-NEXT: fcvt.h.s ft0, ft0
-; CHECKFSGNJ-NEXT: fcvt.s.h ft0, ft0
-; CHECKFSGNJ-NEXT: fneg.s ft0, ft0
-; CHECKFSGNJ-NEXT: fcvt.h.s ft0, ft0
-; CHECKFSGNJ-NEXT: fsh fa0, 8(sp)
-; CHECKFSGNJ-NEXT: fsh ft0, 12(sp)
-; CHECKFSGNJ-NEXT: lbu a0, 9(sp)
-; CHECKFSGNJ-NEXT: lbu a1, 13(sp)
-; CHECKFSGNJ-NEXT: andi a0, a0, 127
-; CHECKFSGNJ-NEXT: andi a1, a1, 128
-; CHECKFSGNJ-NEXT: or a0, a0, a1
-; CHECKFSGNJ-NEXT: sb a0, 9(sp)
-; CHECKFSGNJ-NEXT: flh fa0, 8(sp)
-; CHECKFSGNJ-NEXT: addi sp, sp, 16
-; CHECKFSGNJ-NEXT: ret
-; CHECK64FSGNJ-LABEL: fsgnjn_s:
-; CHECK64FSGNJ: # %bb.0:
-; CHECK64FSGNJ-NEXT: addi sp, sp, -16
-; CHECK64FSGNJ-NEXT: fcvt.s.h ft0, fa1
-; CHECK64FSGNJ-NEXT: fcvt.s.h ft1, fa0
-; CHECK64FSGNJ-NEXT: fadd.s ft0, ft1, ft0
-; CHECK64FSGNJ-NEXT: fcvt.h.s ft0, ft0
-; CHECK64FSGNJ-NEXT: fcvt.s.h ft0, ft0
-; CHECK64FSGNJ-NEXT: fneg.s ft0, ft0
-; CHECK64FSGNJ-NEXT: fcvt.h.s ft0, ft0
-; CHECK64FSGNJ-NEXT: fsh fa0, 0(sp)
-; CHECK64FSGNJ-NEXT: fsh ft0, 8(sp)
-; CHECK64FSGNJ-NEXT: lbu a0, 1(sp)
-; CHECK64FSGNJ-NEXT: lbu a1, 9(sp)
-; CHECK64FSGNJ-NEXT: andi a0, a0, 127
-; CHECK64FSGNJ-NEXT: andi a1, a1, 128
-; CHECK64FSGNJ-NEXT: or a0, a0, a1
-; CHECK64FSGNJ-NEXT: sb a0, 1(sp)
-; CHECK64FSGNJ-NEXT: flh fa0, 0(sp)
-; CHECK64FSGNJ-NEXT: addi sp, sp, 16
-; CHECK64FSGNJ-NEXT: ret
+; RV32IZFHMIN-LABEL: fsgnjn_s:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 4(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 5(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 5(sp)
+; RV32IZFHMIN-NEXT: flh fa5, 4(sp)
+; RV32IZFHMIN-NEXT: fsh fa0, 8(sp)
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV32IZFHMIN-NEXT: lbu a1, 13(sp)
+; RV32IZFHMIN-NEXT: andi a0, a0, 127
+; RV32IZFHMIN-NEXT: andi a1, a1, 128
+; RV32IZFHMIN-NEXT: or a0, a0, a1
+; RV32IZFHMIN-NEXT: sb a0, 9(sp)
+; RV32IZFHMIN-NEXT: flh fa0, 8(sp)
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fsgnjn_s:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -32
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: fsh fa0, 16(sp)
+; RV64IZFHMIN-NEXT: fsh fa5, 24(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 17(sp)
+; RV64IZFHMIN-NEXT: lbu a1, 25(sp)
+; RV64IZFHMIN-NEXT: andi a0, a0, 127
+; RV64IZFHMIN-NEXT: andi a1, a1, 128
+; RV64IZFHMIN-NEXT: or a0, a0, a1
+; RV64IZFHMIN-NEXT: sb a0, 17(sp)
+; RV64IZFHMIN-NEXT: flh fa0, 16(sp)
+; RV64IZFHMIN-NEXT: addi sp, sp, 32
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fsgnjn_s:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a0
+; RV32IZHINXMIN-NEXT: fadd.s a1, a2, a1
+; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV32IZHINXMIN-NEXT: sh a1, 4(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 5(sp)
+; RV32IZHINXMIN-NEXT: xori a1, a1, 128
+; RV32IZHINXMIN-NEXT: sb a1, 5(sp)
+; RV32IZHINXMIN-NEXT: lh a1, 4(sp)
+; RV32IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: sh a1, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a0, 9(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 13(sp)
+; RV32IZHINXMIN-NEXT: andi a0, a0, 127
+; RV32IZHINXMIN-NEXT: andi a1, a1, 128
+; RV32IZHINXMIN-NEXT: or a0, a0, a1
+; RV32IZHINXMIN-NEXT: sb a0, 9(sp)
+; RV32IZHINXMIN-NEXT: lh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fsgnjn_s:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -32
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a0
+; RV64IZHINXMIN-NEXT: fadd.s a1, a2, a1
+; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV64IZHINXMIN-NEXT: sh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 9(sp)
+; RV64IZHINXMIN-NEXT: xori a1, a1, 128
+; RV64IZHINXMIN-NEXT: sb a1, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: sh a0, 16(sp)
+; RV64IZHINXMIN-NEXT: sh a1, 24(sp)
+; RV64IZHINXMIN-NEXT: lbu a0, 17(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 25(sp)
+; RV64IZHINXMIN-NEXT: andi a0, a0, 127
+; RV64IZHINXMIN-NEXT: andi a1, a1, 128
+; RV64IZHINXMIN-NEXT: or a0, a0, a1
+; RV64IZHINXMIN-NEXT: sb a0, 17(sp)
+; RV64IZHINXMIN-NEXT: lh a0, 16(sp)
+; RV64IZHINXMIN-NEXT: addi sp, sp, 32
+; RV64IZHINXMIN-NEXT: ret
%1 = fadd half %a, %b
%2 = fneg half %1
%3 = call half @llvm.copysign.f16(half %a, half %2)
@@ -904,12 +862,12 @@ define half @fabs_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fadd.h fa0, fa4, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fabs_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a0, a0, a1
-; CHECK-ZHINX-NEXT: fabs.h a1, a0
-; CHECK-ZHINX-NEXT: fadd.h a0, a1, a0
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fabs_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
+; CHECKIZHINX-NEXT: fabs.h a1, a0
+; CHECKIZHINX-NEXT: fadd.h a0, a1, a0
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fabs_s:
; RV32I: # %bb.0:
@@ -985,56 +943,81 @@ define half @fabs_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fabs_s:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa0
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: andi a0, a0, 127
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa4, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fabs_s:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa0
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: andi a0, a0, 127
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa4, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fabs_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fabs.s a1, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a1, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fabs_s:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: andi a0, a0, 127
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa4, 12(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fabs_s:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: andi a0, a0, 127
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa4, 8(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fabs_s:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fadd.s a0, a0, a1
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: sh a0, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 13(sp)
+; RV32IZHINXMIN-NEXT: andi a1, a1, 127
+; RV32IZHINXMIN-NEXT: sb a1, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a1, 12(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fadd.s a0, a1, a0
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fabs_s:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fadd.s a0, a0, a1
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 9(sp)
+; RV64IZHINXMIN-NEXT: andi a1, a1, 127
+; RV64IZHINXMIN-NEXT: sb a1, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fadd.s a0, a1, a0
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%1 = fadd half %a, %b
%2 = call half @llvm.fabs.f16(half %1)
%3 = fadd half %2, %1
@@ -1049,10 +1032,10 @@ define half @fmin_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fmin_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fmin.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fmin_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmin.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fmin_s:
; RV32I: # %bb.0:
@@ -1114,20 +1097,13 @@ define half @fmin_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fmin_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmin.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fmin_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmin.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fmin_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmin.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.minnum.f16(half %a, half %b)
ret half %1
}
@@ -1140,10 +1116,10 @@ define half @fmax_s(half %a, half %b) nounwind {
; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fmax_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fmax.h a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fmax_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmax.h a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fmax_s:
; RV32I: # %bb.0:
@@ -1205,20 +1181,13 @@ define half @fmax_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fmax_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmax.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fmax_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmax.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fmax_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmax.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.maxnum.f16(half %a, half %b)
ret half %1
}
@@ -1231,10 +1200,10 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fmadd_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fmadd.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fmadd_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fmadd_s:
; RV32I: # %bb.0:
@@ -1311,22 +1280,14 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fmadd_s:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fmadd_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fmadd_s:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
ret half %1
}
@@ -1339,11 +1300,11 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fmsub_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a2, a2, zero
-; CHECK-ZHINX-NEXT: fmsub.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fmsub_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
+; CHECKIZHINX-NEXT: fmsub.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0:
@@ -1433,59 +1394,83 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fmsub_s:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV32-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fmsub_s:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV64-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fmsub_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fadd.s a2, a2, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fneg.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fmsub_s:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV32IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fmsub_s:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV64IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fmsub_s:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fadd.s a2, a2, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a2, a2
+; RV32IZHINXMIN-NEXT: sh a2, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a2, 13(sp)
+; RV32IZHINXMIN-NEXT: xori a2, a2, 128
+; RV32IZHINXMIN-NEXT: sb a2, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a2, 12(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fmsub_s:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fadd.s a2, a2, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a2, a2
+; RV64IZHINXMIN-NEXT: sh a2, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a2, 9(sp)
+; RV64IZHINXMIN-NEXT: xori a2, a2, 128
+; RV64IZHINXMIN-NEXT: sb a2, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a2, 8(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor
%negc = fsub half -0.0, %c_
%1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
@@ -1501,12 +1486,12 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmadd.h fa0, fa4, fa1, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmadd_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a0, a0, zero
-; CHECK-ZHINX-NEXT: fadd.h a2, a2, zero
-; CHECK-ZHINX-NEXT: fnmadd.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmadd_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
+; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
+; CHECKIZHINX-NEXT: fnmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0:
@@ -1624,81 +1609,115 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fnmadd_s:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV32-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa4, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV32-FSGNJ-NEXT: fmadd.s fa5, fa4, fa3, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fnmadd_s:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV64-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa4, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV64-FSGNJ-NEXT: fmadd.s fa5, fa4, fa3, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmadd_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fadd.s a2, a2, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fneg.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fneg.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fnmadd_s:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV32IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 9(sp)
+; RV32IZFHMIN-NEXT: flh fa4, 8(sp)
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV32IZFHMIN-NEXT: fmadd.s fa5, fa4, fa3, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fnmadd_s:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV64IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 0(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 1(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 1(sp)
+; RV64IZFHMIN-NEXT: flh fa4, 0(sp)
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV64IZFHMIN-NEXT: fmadd.s fa5, fa4, fa3, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fnmadd_s:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fadd.s a0, a0, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: lbu a0, 9(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fadd.s a2, a2, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a2, a2
+; RV32IZHINXMIN-NEXT: xori a0, a0, 128
+; RV32IZHINXMIN-NEXT: sb a0, 9(sp)
+; RV32IZHINXMIN-NEXT: lh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: sh a2, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a2, 13(sp)
+; RV32IZHINXMIN-NEXT: xori a2, a2, 128
+; RV32IZHINXMIN-NEXT: sb a2, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a2, 12(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fnmadd_s:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fadd.s a0, a0, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: sh a0, 0(sp)
+; RV64IZHINXMIN-NEXT: lbu a0, 1(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fadd.s a2, a2, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a2, a2
+; RV64IZHINXMIN-NEXT: xori a0, a0, 128
+; RV64IZHINXMIN-NEXT: sb a0, 1(sp)
+; RV64IZHINXMIN-NEXT: lh a0, 0(sp)
+; RV64IZHINXMIN-NEXT: sh a2, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a2, 9(sp)
+; RV64IZHINXMIN-NEXT: xori a2, a2, 128
+; RV64IZHINXMIN-NEXT: sb a2, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a2, 8(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%a_ = fadd half 0.0, %a
%c_ = fadd half 0.0, %c
%nega = fsub half -0.0, %a_
@@ -1716,12 +1735,12 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmadd.h fa0, fa4, fa0, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmadd_s_2:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a1, a1, zero
-; CHECK-ZHINX-NEXT: fadd.h a2, a2, zero
-; CHECK-ZHINX-NEXT: fnmadd.h a0, a1, a0, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmadd_s_2:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
+; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
+; CHECKIZHINX-NEXT: fnmadd.h a0, a1, a0, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0:
@@ -1839,81 +1858,115 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fnmadd_s_2:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV32-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa4, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV32-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fnmadd_s_2:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV64-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa4, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa4
-; CHECK-RV64-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmadd_s_2:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fadd.s a1, a1, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fadd.s a2, a2, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fneg.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fneg.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fnmadd_s_2:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV32IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 9(sp)
+; RV32IZFHMIN-NEXT: flh fa4, 8(sp)
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV32IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fnmadd_s_2:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV64IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 0(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 1(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 1(sp)
+; RV64IZFHMIN-NEXT: flh fa4, 0(sp)
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa4
+; RV64IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fnmadd_s_2:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV32IZHINXMIN-NEXT: sh a1, 8(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 9(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fadd.s a2, a2, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a2, a2
+; RV32IZHINXMIN-NEXT: xori a1, a1, 128
+; RV32IZHINXMIN-NEXT: sb a1, 9(sp)
+; RV32IZHINXMIN-NEXT: lh a1, 8(sp)
+; RV32IZHINXMIN-NEXT: sh a2, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a2, 13(sp)
+; RV32IZHINXMIN-NEXT: xori a2, a2, 128
+; RV32IZHINXMIN-NEXT: sb a2, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a2, 12(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fnmadd_s_2:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV64IZHINXMIN-NEXT: sh a1, 0(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 1(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fadd.s a2, a2, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a2, a2
+; RV64IZHINXMIN-NEXT: xori a1, a1, 128
+; RV64IZHINXMIN-NEXT: sb a1, 1(sp)
+; RV64IZHINXMIN-NEXT: lh a1, 0(sp)
+; RV64IZHINXMIN-NEXT: sh a2, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a2, 9(sp)
+; RV64IZHINXMIN-NEXT: xori a2, a2, 128
+; RV64IZHINXMIN-NEXT: sb a2, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a2, 8(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%b_ = fadd half 0.0, %b
%c_ = fadd half 0.0, %c
%negb = fsub half -0.0, %b_
@@ -1941,12 +1994,12 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fneg.h fa0, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmadd_s_3:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fmadd.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: lui a1, 1048568
-; CHECK-ZHINX-NEXT: xor a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmadd_s_3:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: lui a1, 1048568
+; CHECKIZHINX-NEXT: xor a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_3:
; RV32I: # %bb.0:
@@ -2018,58 +2071,48 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fnmadd_s_3:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV32-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa0, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fnmadd_s_3:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV64-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa0, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-;
-; CHECKZHINXMIN-LABEL: fnmadd_s_3:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: lui a1, 1048568
-; CHECKZHINXMIN-NEXT: xor a0, a0, a1
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmadd_s_3:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: lui a1, 1048568
-; CHECK-ZHINXMIN-NEXT: xor a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fnmadd_s_3:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV32IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa0, 12(sp)
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fnmadd_s_3:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV64IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa0, 8(sp)
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; CHECKIZHINXMIN-LABEL: fnmadd_s_3:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: lui a1, 1048568
+; CHECKIZHINXMIN-NEXT: xor a0, a0, a1
+; CHECKIZHINXMIN-NEXT: ret
%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
%neg = fneg half %1
ret half %neg
@@ -2092,12 +2135,12 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmadd_nsz:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fmadd.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: lui a1, 1048568
-; CHECK-ZHINX-NEXT: xor a0, a0, a1
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmadd_nsz:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: lui a1, 1048568
+; CHECKIZHINX-NEXT: xor a0, a0, a1
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmadd_nsz:
; RV32I: # %bb.0:
@@ -2169,58 +2212,48 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fnmadd_nsz:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV32-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa0, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fnmadd_nsz:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV64-FSGNJ-NEXT: fmadd.s fa5, fa3, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa0, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-;
-; CHECKZHINXMIN-LABEL: fnmadd_nsz:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: lui a1, 1048568
-; CHECKZHINXMIN-NEXT: xor a0, a0, a1
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmadd_nsz:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: lui a1, 1048568
-; CHECK-ZHINXMIN-NEXT: xor a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fnmadd_nsz:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV32IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa0, 12(sp)
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fnmadd_nsz:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV64IZFHMIN-NEXT: fmadd.s fa5, fa3, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa0, 8(sp)
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; CHECKIZHINXMIN-LABEL: fnmadd_nsz:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: lui a1, 1048568
+; CHECKIZHINXMIN-NEXT: xor a0, a0, a1
+; CHECKIZHINXMIN-NEXT: ret
%1 = call nsz half @llvm.fma.f16(half %a, half %b, half %c)
%neg = fneg nsz half %1
ret half %neg
@@ -2234,11 +2267,11 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmsub.h fa0, fa5, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmsub_s:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a0, a0, zero
-; CHECK-ZHINX-NEXT: fnmsub.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmsub_s:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
+; CHECKIZHINX-NEXT: fnmsub.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0:
@@ -2326,59 +2359,83 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fnmsub_s:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV32-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa2
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fmadd.s fa5, fa5, fa3, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fnmsub_s:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV64-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa2
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fmadd.s fa5, fa5, fa3, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmsub_s:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fneg.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fnmsub_s:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV32IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa2
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fmadd.s fa5, fa5, fa3, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fnmsub_s:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV64IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa2
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fmadd.s fa5, fa5, fa3, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fnmsub_s:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fadd.s a0, a0, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: sh a0, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a0, 13(sp)
+; RV32IZHINXMIN-NEXT: xori a0, a0, 128
+; RV32IZHINXMIN-NEXT: sb a0, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a0, 12(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fnmsub_s:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fadd.s a0, a0, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a0, 9(sp)
+; RV64IZHINXMIN-NEXT: xori a0, a0, 128
+; RV64IZHINXMIN-NEXT: sb a0, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a0, 8(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%a_ = fadd half 0.0, %a
%nega = fsub half -0.0, %a_
%1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
@@ -2393,11 +2450,11 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmsub.h fa0, fa5, fa0, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmsub_s_2:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a1, a1, zero
-; CHECK-ZHINX-NEXT: fnmsub.h a0, a1, a0, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmsub_s_2:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
+; CHECKIZHINX-NEXT: fnmsub.h a0, a1, a0, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0:
@@ -2487,59 +2544,83 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fnmsub_s_2:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV32-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa2
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fmadd.s fa5, fa3, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fnmsub_s_2:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa1
-; CHECK-RV64-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa2
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa0
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fmadd.s fa5, fa3, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmsub_s_2:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fadd.s a1, a1, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fneg.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fnmsub_s_2:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV32IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa2
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fmadd.s fa5, fa3, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fnmsub_s_2:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; RV64IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa2
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa0
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fmadd.s fa5, fa3, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fnmsub_s_2:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV32IZHINXMIN-NEXT: sh a1, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a1, 13(sp)
+; RV32IZHINXMIN-NEXT: xori a1, a1, 128
+; RV32IZHINXMIN-NEXT: sb a1, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a1, 12(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fnmsub_s_2:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV64IZHINXMIN-NEXT: sh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a1, 9(sp)
+; RV64IZHINXMIN-NEXT: xori a1, a1, 128
+; RV64IZHINXMIN-NEXT: sb a1, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a1, 8(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fmadd.s a0, a0, a1, a2
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%b_ = fadd half 0.0, %b
%negb = fsub half -0.0, %b_
%1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
@@ -2552,10 +2633,10 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fmadd_s_contract:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fmadd.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fmadd_s_contract:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fmadd_s_contract:
; RV32I: # %bb.0:
@@ -2645,28 +2726,17 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fmadd_s_contract:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a2
-; CHECKZHINXMIN-NEXT: fadd.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fmadd_s_contract:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a2
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fmadd_s_contract:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmul.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a2
+; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%1 = fmul contract half %a, %b
%2 = fadd contract half %1, %c
ret half %2
@@ -2680,11 +2750,11 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fmsub_s_contract:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a2, a2, zero
-; CHECK-ZHINX-NEXT: fmsub.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fmsub_s_contract:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
+; CHECKIZHINX-NEXT: fmsub.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0:
@@ -2790,34 +2860,20 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fmsub_s_contract:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECKZHINXMIN-NEXT: fadd.s a2, a2, zero
-; CHECKZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a2
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fsub.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fmsub_s_contract:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fadd.s a2, a2, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fsub.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fmsub_s_contract:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
+; CHECKIZHINXMIN-NEXT: fadd.s a2, a2, zero
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a2, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmul.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fsub.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor
%1 = fmul contract half %a, %b
%2 = fsub contract half %1, %c_
@@ -2834,13 +2890,13 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmadd.h fa0, fa4, fa3, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmadd_s_contract:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a0, a0, zero
-; CHECK-ZHINX-NEXT: fadd.h a1, a1, zero
-; CHECK-ZHINX-NEXT: fadd.h a2, a2, zero
-; CHECK-ZHINX-NEXT: fnmadd.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmadd_s_contract:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
+; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
+; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
+; CHECKIZHINX-NEXT: fnmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0:
@@ -2964,86 +3020,119 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fnmadd_s_contract:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV32-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa1
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa3, fa3, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa3, fa3
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa3, fa3
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fmul.s fa5, fa5, fa3
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV32-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa3, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa3
-; CHECK-RV32-FSGNJ-NEXT: fsub.s fa5, fa4, fa5
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fnmadd_s_contract:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa0
-; CHECK-RV64-FSGNJ-NEXT: fmv.w.x fa4, zero
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa1
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa3, fa3, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa3, fa3
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa3, fa3
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fmul.s fa5, fa5, fa3
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa2
-; CHECK-RV64-FSGNJ-NEXT: xori a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa3, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fadd.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa3
-; CHECK-RV64-FSGNJ-NEXT: fsub.s fa5, fa4, fa5
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmadd_s_contract:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fadd.s a1, a1, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a2, a2
-; CHECK-ZHINXMIN-NEXT: fadd.s a2, a2, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a2, a2
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fneg.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a2
-; CHECK-ZHINXMIN-NEXT: fsub.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: fnmadd_s_contract:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV32IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa1
+; RV32IZFHMIN-NEXT: fadd.s fa3, fa3, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa3, fa3
+; RV32IZFHMIN-NEXT: fcvt.s.h fa3, fa3
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fmul.s fa5, fa5, fa3
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fsh fa5, 12(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV32IZFHMIN-NEXT: xori a0, a0, 128
+; RV32IZFHMIN-NEXT: sb a0, 13(sp)
+; RV32IZFHMIN-NEXT: flh fa3, 12(sp)
+; RV32IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa3
+; RV32IZFHMIN-NEXT: fsub.s fa5, fa4, fa5
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fnmadd_s_contract:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; RV64IZFHMIN-NEXT: fmv.w.x fa4, zero
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa1
+; RV64IZFHMIN-NEXT: fadd.s fa3, fa3, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa3, fa3
+; RV64IZFHMIN-NEXT: fcvt.s.h fa3, fa3
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fmul.s fa5, fa5, fa3
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa2
+; RV64IZFHMIN-NEXT: xori a0, a0, 128
+; RV64IZFHMIN-NEXT: sb a0, 9(sp)
+; RV64IZFHMIN-NEXT: flh fa3, 8(sp)
+; RV64IZFHMIN-NEXT: fadd.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa3
+; RV64IZFHMIN-NEXT: fsub.s fa5, fa4, fa5
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fnmadd_s_contract:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fadd.s a0, a0, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fmul.s a0, a0, a1
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: sh a0, 12(sp)
+; RV32IZHINXMIN-NEXT: lbu a0, 13(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a2
+; RV32IZHINXMIN-NEXT: xori a0, a0, 128
+; RV32IZHINXMIN-NEXT: sb a0, 13(sp)
+; RV32IZHINXMIN-NEXT: lh a0, 12(sp)
+; RV32IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV32IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fsub.s a0, a0, a1
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fnmadd_s_contract:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fadd.s a0, a0, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fmul.s a0, a0, a1
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV64IZHINXMIN-NEXT: lbu a0, 9(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a2
+; RV64IZHINXMIN-NEXT: xori a0, a0, 128
+; RV64IZHINXMIN-NEXT: sb a0, 9(sp)
+; RV64IZHINXMIN-NEXT: lh a0, 8(sp)
+; RV64IZHINXMIN-NEXT: fadd.s a1, a1, zero
+; RV64IZHINXMIN-NEXT: fcvt.h.s a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fsub.s a0, a0, a1
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%a_ = fadd half 0.0, %a ; avoid negation using xor
%b_ = fadd half 0.0, %b ; avoid negation using xor
%c_ = fadd half 0.0, %c ; avoid negation using xor
@@ -3062,12 +3151,12 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmsub.h fa0, fa4, fa5, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fnmsub_s_contract:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fadd.h a0, a0, zero
-; CHECK-ZHINX-NEXT: fadd.h a1, a1, zero
-; CHECK-ZHINX-NEXT: fnmsub.h a0, a0, a1, a2
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fnmsub_s_contract:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
+; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
+; CHECKIZHINX-NEXT: fnmsub.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0:
@@ -3190,40 +3279,23 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKZHINXMIN-LABEL: fnmsub_s_contract:
-; CHECKZHINXMIN: # %bb.0:
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fadd.s a0, a0, zero
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fadd.s a1, a1, zero
-; CHECKZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKZHINXMIN-NEXT: fcvt.s.h a1, a2
-; CHECKZHINXMIN-NEXT: fsub.s a0, a1, a0
-; CHECKZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKZHINXMIN-NEXT: ret
-; CHECK-ZHINXMIN-LABEL: fnmsub_s_contract:
-; CHECK-ZHINXMIN: # %bb.0:
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fadd.s a0, a0, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fadd.s a1, a1, zero
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fmul.s a0, a0, a1
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.s.h a1, a2
-; CHECK-ZHINXMIN-NEXT: fsub.s a0, a1, a0
-; CHECK-ZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECK-ZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-LABEL: fnmsub_s_contract:
+; CHECKIZHINXMIN: # %bb.0:
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, zero
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fadd.s a1, a1, zero
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fmul.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a2
+; CHECKIZHINXMIN-NEXT: fsub.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: ret
%a_ = fadd half 0.0, %a ; avoid negation using xor
%b_ = fadd half 0.0, %b ; avoid negation using xor
%1 = fmul contract half %a_, %b_
@@ -3237,10 +3309,10 @@ define half @fsgnjx_f16(half %x, half %y) nounwind {
; CHECKIZFH-NEXT: fsgnjx.h fa0, fa1, fa0
; CHECKIZFH-NEXT: ret
;
-; CHECK-ZHINX-LABEL: fsgnjx_f16:
-; CHECK-ZHINX: # %bb.0:
-; CHECK-ZHINX-NEXT: fsgnjx.h a0, a1, a0
-; CHECK-ZHINX-NEXT: ret
+; CHECKIZHINX-LABEL: fsgnjx_f16:
+; CHECKIZHINX: # %bb.0:
+; CHECKIZHINX-NEXT: fsgnjx.h a0, a1, a0
+; CHECKIZHINX-NEXT: ret
;
; RV32I-LABEL: fsgnjx_f16:
; RV32I: # %bb.0:
@@ -3294,47 +3366,89 @@ define half @fsgnjx_f16(half %x, half %y) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECK-RV32-FSGNJ-LABEL: fsgnjx_f16:
-; CHECK-RV32-FSGNJ: # %bb.0:
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV32-FSGNJ-NEXT: lui a0, %hi(.LCPI23_0)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
-; CHECK-RV32-FSGNJ-NEXT: fsh fa0, 12(sp)
-; CHECK-RV32-FSGNJ-NEXT: fsh fa5, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a0, 13(sp)
-; CHECK-RV32-FSGNJ-NEXT: lbu a1, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: andi a0, a0, 128
-; CHECK-RV32-FSGNJ-NEXT: andi a1, a1, 127
-; CHECK-RV32-FSGNJ-NEXT: or a0, a1, a0
-; CHECK-RV32-FSGNJ-NEXT: sb a0, 9(sp)
-; CHECK-RV32-FSGNJ-NEXT: flh fa5, 8(sp)
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV32-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV32-FSGNJ-NEXT: fmul.s fa5, fa5, fa4
-; CHECK-RV32-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV32-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV32-FSGNJ-NEXT: ret
-;
-; CHECK-RV64-FSGNJ-LABEL: fsgnjx_f16:
-; CHECK-RV64-FSGNJ: # %bb.0:
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, -16
-; CHECK-RV64-FSGNJ-NEXT: lui a0, %hi(.LCPI23_0)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
-; CHECK-RV64-FSGNJ-NEXT: fsh fa0, 8(sp)
-; CHECK-RV64-FSGNJ-NEXT: fsh fa5, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a0, 9(sp)
-; CHECK-RV64-FSGNJ-NEXT: lbu a1, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: andi a0, a0, 128
-; CHECK-RV64-FSGNJ-NEXT: andi a1, a1, 127
-; CHECK-RV64-FSGNJ-NEXT: or a0, a1, a0
-; CHECK-RV64-FSGNJ-NEXT: sb a0, 1(sp)
-; CHECK-RV64-FSGNJ-NEXT: flh fa5, 0(sp)
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa4, fa1
-; CHECK-RV64-FSGNJ-NEXT: fcvt.s.h fa5, fa5
-; CHECK-RV64-FSGNJ-NEXT: fmul.s fa5, fa5, fa4
-; CHECK-RV64-FSGNJ-NEXT: fcvt.h.s fa0, fa5
-; CHECK-RV64-FSGNJ-NEXT: addi sp, sp, 16
-; CHECK-RV64-FSGNJ-NEXT: ret
+; RV32IZFHMIN-LABEL: fsgnjx_f16:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: addi sp, sp, -16
+; RV32IZFHMIN-NEXT: lui a0, %hi(.LCPI23_0)
+; RV32IZFHMIN-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
+; RV32IZFHMIN-NEXT: fsh fa0, 12(sp)
+; RV32IZFHMIN-NEXT: fsh fa5, 8(sp)
+; RV32IZFHMIN-NEXT: lbu a0, 13(sp)
+; RV32IZFHMIN-NEXT: lbu a1, 9(sp)
+; RV32IZFHMIN-NEXT: andi a0, a0, 128
+; RV32IZFHMIN-NEXT: andi a1, a1, 127
+; RV32IZFHMIN-NEXT: or a0, a1, a0
+; RV32IZFHMIN-NEXT: sb a0, 9(sp)
+; RV32IZFHMIN-NEXT: flh fa5, 8(sp)
+; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV32IZFHMIN-NEXT: fmul.s fa5, fa5, fa4
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: addi sp, sp, 16
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: fsgnjx_f16:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: addi sp, sp, -16
+; RV64IZFHMIN-NEXT: lui a0, %hi(.LCPI23_0)
+; RV64IZFHMIN-NEXT: flh fa5, %lo(.LCPI23_0)(a0)
+; RV64IZFHMIN-NEXT: fsh fa0, 8(sp)
+; RV64IZFHMIN-NEXT: fsh fa5, 0(sp)
+; RV64IZFHMIN-NEXT: lbu a0, 9(sp)
+; RV64IZFHMIN-NEXT: lbu a1, 1(sp)
+; RV64IZFHMIN-NEXT: andi a0, a0, 128
+; RV64IZFHMIN-NEXT: andi a1, a1, 127
+; RV64IZFHMIN-NEXT: or a0, a1, a0
+; RV64IZFHMIN-NEXT: sb a0, 1(sp)
+; RV64IZFHMIN-NEXT: flh fa5, 0(sp)
+; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1
+; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5
+; RV64IZFHMIN-NEXT: fmul.s fa5, fa5, fa4
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: addi sp, sp, 16
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: fsgnjx_f16:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: addi sp, sp, -16
+; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0)
+; RV32IZHINXMIN-NEXT: lh a2, %lo(.LCPI23_0)(a2)
+; RV32IZHINXMIN-NEXT: sh a0, 12(sp)
+; RV32IZHINXMIN-NEXT: sh a2, 8(sp)
+; RV32IZHINXMIN-NEXT: lbu a0, 13(sp)
+; RV32IZHINXMIN-NEXT: lbu a2, 9(sp)
+; RV32IZHINXMIN-NEXT: andi a0, a0, 128
+; RV32IZHINXMIN-NEXT: andi a2, a2, 127
+; RV32IZHINXMIN-NEXT: or a0, a2, a0
+; RV32IZHINXMIN-NEXT: sb a0, 9(sp)
+; RV32IZHINXMIN-NEXT: lh a0, 8(sp)
+; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT: fmul.s a0, a0, a1
+; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT: addi sp, sp, 16
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: fsgnjx_f16:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: addi sp, sp, -16
+; RV64IZHINXMIN-NEXT: lui a2, %hi(.LCPI23_0)
+; RV64IZHINXMIN-NEXT: lh a2, %lo(.LCPI23_0)(a2)
+; RV64IZHINXMIN-NEXT: sh a0, 8(sp)
+; RV64IZHINXMIN-NEXT: sh a2, 0(sp)
+; RV64IZHINXMIN-NEXT: lbu a0, 9(sp)
+; RV64IZHINXMIN-NEXT: lbu a2, 1(sp)
+; RV64IZHINXMIN-NEXT: andi a0, a0, 128
+; RV64IZHINXMIN-NEXT: andi a2, a2, 127
+; RV64IZHINXMIN-NEXT: or a0, a2, a0
+; RV64IZHINXMIN-NEXT: sb a0, 1(sp)
+; RV64IZHINXMIN-NEXT: lh a0, 0(sp)
+; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT: fmul.s a0, a0, a1
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: addi sp, sp, 16
+; RV64IZHINXMIN-NEXT: ret
%z = call half @llvm.copysign.f16(half 1.0, half %x)
%mul = fmul half %z, %y
ret half %mul
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