[llvm] 02eb03d - [RISCV] Use DwarfRegAlias instead of DwarfRegNum for 32-bit and 64-bit FP registers.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-08-30T16:12:37-07:00
New Revision: 02eb03d5e0fef68a37751bd4865eff98c0e20a8c

URL: https://github.com/llvm/llvm-project/commit/02eb03d5e0fef68a37751bd4865eff98c0e20a8c
DIFF: https://github.com/llvm/llvm-project/commit/02eb03d5e0fef68a37751bd4865eff98c0e20a8c.diff

LOG: [RISCV] Use DwarfRegAlias instead of DwarfRegNum for 32-bit and 64-bit FP registers.

There should only be one register that specifies a particular
DwarfRegNum.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index efdf6bebfce301..73649129e4f93f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -234,12 +234,12 @@ let RegAltNameIndices = [ABIRegAltName] in {
 
   foreach Index = 0-31 in {
     def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>,
-      DwarfRegNum<[!add(Index, 32)]>;
+      DwarfRegAlias<!cast<Register>("F"#Index#"_H")>;
   }
 
   foreach Index = 0-31 in {
     def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
-      DwarfRegNum<[!add(Index, 32)]>;
+      DwarfRegAlias<!cast<Register>("F"#Index#"_H")>;
   }
 }