[llvm] [DL] Invert `getTypeStoreSize` bytes-bits relationship to avoid `divideCeil` (PR #106757)

[Antonio Frighetto via llvm-commits]

================
@@ -433,7 +434,10 @@ class DataLayout {
   ///
   /// For example, returns 40 for i36 and 80 for x86_fp80.
   TypeSize getTypeStoreSizeInBits(Type *Ty) const {
-    return 8 * getTypeStoreSize(Ty);
+    TypeSize BaseSize = getTypeSizeInBits(Ty);
+    uint64_t AlignedSizeInBits =
+        alignToPowerOf2(BaseSize.getKnownMinValue(), sizeof(uint64_t));
----------------
antoniofrighetto wrote:

Leftover from a copy-paste, updated, thanks.

https://github.com/llvm/llvm-project/pull/106757