[llvm] [AMDGPU][True16][MC] 16bit vsrc and vdst support in MC (PR #104510)

[Brox Chen via llvm-commits]

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@@ -22,23 +22,6 @@ body:             |
     %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %4, implicit $exec
 ...
 
-# Needs extra shift instruction to select hi 16 bits
----
-name:            cvt_hi_f32_f16
-body:             |
-  bb.0:
-    ; GCN-LABEL: name: cvt_hi_f32_f16
-    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
-    ; GCN-NEXT: [[V_CVT_F16_U16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F16_U16_e64 [[DEF]], 0, 0, implicit $mode, implicit $exec
-    ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
-    ; GCN-NEXT: [[V_LSHRREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, [[V_CVT_F16_U16_e64_]], implicit $exec
-    ; GCN-NEXT: [[V_CVT_F32_F16_t16_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_t16_e64 0, [[V_LSHRREV_B32_e64_]], 0, 0, implicit $mode, implicit $exec
-    %0:vgpr_32 = IMPLICIT_DEF
-    %1:vgpr_32 = V_CVT_F16_U16_e64 %0:vgpr_32, 0, 0, implicit $mode, implicit $exec
----------------
broxigarchen wrote:

The fake16 flow is working. The reason I marked it as XFAIL is because the name of V_CVT_F16_U16_fake16 is currently  V_CVT_F16_U16_t16 (t16 but use fake16 profile).

I can use V_CVT_F16_U16_t16  in the mir file to get this test pass for now and I can update the V_CVT_F16_U16 later

https://github.com/llvm/llvm-project/pull/104510