[llvm] [RISCV] Add scalable vector patterns for vfwmaccbf16.v{v,f} (PR #106771)

[Craig Topper via llvm-commits]

topperc wrote:

> For some reason nxv1f32 gets type-legalized to nxv2f32, I haven't looked into why this happens yet.

You didn't enable V so you got Zve32f. We don't allow the nxv1 types because ELEN=32 doesn't have LMUL=1/2 SEW=32.

https://github.com/llvm/llvm-project/pull/106771