[llvm] d0d0e12 - [AArch64] Fix a presumed typo in isFPImmLegal limit. NFC (#106716)

[via llvm-commits]

Author: Marina Taylor
Date: 2024-08-30T18:48:08+01:00
New Revision: d0d0e125a66b7c7921ad82c13c893bf592f071ba

URL: https://github.com/llvm/llvm-project/commit/d0d0e125a66b7c7921ad82c13c893bf592f071ba
DIFF: https://github.com/llvm/llvm-project/commit/d0d0e125a66b7c7921ad82c13c893bf592f071ba.diff

LOG: [AArch64] Fix a presumed typo in isFPImmLegal limit. NFC (#106716)

The worst possible case for a double literal goes like:

```
  mov ...
  movk ..., lsl #16
  movk ..., lsl #32
  movk ..., lsl #48
  fmov ...
```

The limit of 5 in the code gives the impression that `Insn` includes all
instructions including the `fmov`, but that's not true. It only counts
the integer moves. This led me astray on some other work in this area.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 28ad0abf25703b..11aca69db0a148 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11463,7 +11463,9 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
     // movw+movk is fused). So we limit up to 2 instrdduction at most.
     SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
     AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(), Insn);
-    unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 5 : 2));
+    assert(Insn.size() <= 4 &&
+           "Should be able to build any value with at most 4 moves");
+    unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 4 : 2));
     IsLegal = Insn.size() <= Limit;
   }