[llvm] [AArch64] Fix sched model of Neoverse N2 (PR #106376)

[via llvm-commits]

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@@ -858,7 +858,7 @@ def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[SDQ]l$",
                                            "^LDUR[BHSDQ]i$")>;
 
 // Load vector reg, immed post-index
-def : InstRW<[N2Write_6cyc_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
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FLZ101 wrote:

Sure.

https://github.com/llvm/llvm-project/pull/106376