[llvm] [RISCV] Check VL dominates and potentially move in tryReduceVL (PR #106753)

[Luke Lau via llvm-commits]

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@@ -456,6 +460,26 @@ static bool dominates(MachineBasicBlock::const_iterator A,
   return &*I == A;
 }
 
+/// If the register in \p MO doesn't dominate \p Src, try to move \p Src so it
+/// does. Returns false if doesn't dominate and we can't move. \p MO must be in
+/// the same basic block as \Src.
+bool RISCVVectorPeephole::ensureDominates(const MachineOperand &MO,
+                                          MachineInstr &Src) const {
+  assert(MO.getParent()->getParent() == Src.getParent());
+  if (!MO.isReg() || MO.getReg() == RISCV::NoRegister)
+    return true;
+
+  MachineInstr *Def = MRI->getVRegDef(MO.getReg());
+  if (Def->getParent() == Src.getParent() && !dominates(Def, Src)) {
+    if (!isSafeToMove(Src, *Def->getNextNode()))
+      return false;
+    // FIXME: Update V0Defs
----------------
lukel97 wrote:

V0Defs stores the current definition of V0 at each instruction, so this is about updating the current value at Src if we move it.

isSafeToMove checks that any physical register uses aren't clobbered, so if Src doesn't use V0 then it might be moved past a new V0 def.

So masked pseudos won't get moved currently and I don't think we miscompile anything, but we probably do our bookkeeping here anyway.

https://github.com/llvm/llvm-project/pull/106753