[llvm] Fix unassigned add handling in aarch64 (PR #86636)

[Yusuke Abe via llvm-commits]

https://github.com/chansuke updated https://github.com/llvm/llvm-project/pull/86636

>From e973680b1528a26af0af606b3a96ea0438685604 Mon Sep 17 00:00:00 2001
From: chansuke <moonset20 at gmail.com>
Date: Thu, 20 Jun 2024 17:22:06 +0900
Subject: [PATCH] Fix unassigned add handling in aarch64

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b0a906743f29ff..f15bd39f74ae57 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5236,6 +5236,13 @@ SDValue DAGCombiner::visitAVG(SDNode *N) {
           DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getAllOnesConstant(DL, VT)));
   }
 
+  // Fold avgfloors(x,y) -> avgflooru(x,y) if both x and y are non-negative
+  if (Opcode == ISD::AVGFLOORS && !hasOperation(ISD::AVGFLOORS, VT) &&
+      (!LegalOperations || hasOperation(ISD::AVGFLOORU, VT))) {
+    if (DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
+      return DAG.getNode(ISD::AVGFLOORU, DL, VT, N0, N1);
+  }
+
   return SDValue();
 }