[llvm] [LV][VPlan] Add initial support for CSA vectorization (PR #106560)

[Michael Maitland via llvm-commits]

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@@ -1985,6 +1985,11 @@ bool RISCVTTIImpl::isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
                   C2.ScaleCost, C2.ImmCost, C2.SetupCost);
 }
 
+bool RISCVTTIImpl::enableCSAVectorization() const {
+  return ST->hasVInstructions() &&
+         ST->getProcFamily() == RISCVSubtarget::SiFive7;
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michaelmaitland wrote:

We have measured it on a sifive7 cpu and found that it was beneficial to have enabled by default. This was not the case for all microarchitectures that we tested. I think it would be a good idea to let cpus opt into enabling this by default, at least until the feature becomes more mature.

https://github.com/llvm/llvm-project/pull/106560