[llvm] [M68k] always use movem for register spills (PR #106715)
Janis Heims via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 30 07:14:50 PDT 2024
https://github.com/TechnoElf updated https://github.com/llvm/llvm-project/pull/106715
>From b3f427b354a7baa6c3ed255e1cadc9d339d61458 Mon Sep 17 00:00:00 2001
From: TechnoElf <technoelf at undertheprinter.com>
Date: Fri, 30 Aug 2024 13:41:21 +0200
Subject: [PATCH] [M68k] always use movem for register spills / spill 8 bit
registers into 16 bit slots
---
llvm/lib/Target/M68k/M68kExpandPseudo.cpp | 16 +++--------
llvm/lib/Target/M68k/M68kInstrData.td | 4 ---
llvm/lib/Target/M68k/M68kInstrInfo.cpp | 34 ++++++++++-------------
llvm/lib/Target/M68k/M68kRegisterInfo.td | 26 +++++++++++++++++
llvm/test/CodeGen/M68k/PR57660.ll | 22 +++++++--------
5 files changed, 55 insertions(+), 47 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
index c7fdd7d7c35023..1ba265a60c3d60 100644
--- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
+++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
@@ -193,31 +193,23 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case M68k::MOV8dc:
return TII->ExpandCCR(MIB, /*IsToCCR=*/false);
- case M68k::MOVM8jm_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false);
case M68k::MOVM16jm_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false);
+ return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16jm), /*IsRM=*/false);
case M68k::MOVM32jm_P:
return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false);
- case M68k::MOVM8pm_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32pm), /*IsRM=*/false);
case M68k::MOVM16pm_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32pm), /*IsRM=*/false);
+ return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16pm), /*IsRM=*/false);
case M68k::MOVM32pm_P:
return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32pm), /*IsRM=*/false);
- case M68k::MOVM8mj_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true);
case M68k::MOVM16mj_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true);
+ return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16mj), /*IsRM=*/true);
case M68k::MOVM32mj_P:
return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true);
- case M68k::MOVM8mp_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true);
case M68k::MOVM16mp_P:
- return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true);
+ return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16mp), /*IsRM=*/true);
case M68k::MOVM32mp_P:
return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true);
diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
index dc777a933e2786..48aa8aeb667db6 100644
--- a/llvm/lib/Target/M68k/M68kInstrData.td
+++ b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -337,20 +337,16 @@ class MxMOVEM_RM_Pseudo<MxType TYPE, MxOperand MEMOp>
: MxPseudo<(outs TYPE.ROp:$dst), (ins MEMOp:$src)>;
// Mem <- Reg
-def MOVM8jm_P : MxMOVEM_MR_Pseudo<MxType8d, MxType8.JOp>;
def MOVM16jm_P : MxMOVEM_MR_Pseudo<MxType16r, MxType16.JOp>;
def MOVM32jm_P : MxMOVEM_MR_Pseudo<MxType32r, MxType32.JOp>;
-def MOVM8pm_P : MxMOVEM_MR_Pseudo<MxType8d, MxType8.POp>;
def MOVM16pm_P : MxMOVEM_MR_Pseudo<MxType16r, MxType16.POp>;
def MOVM32pm_P : MxMOVEM_MR_Pseudo<MxType32r, MxType32.POp>;
// Reg <- Mem
-def MOVM8mj_P : MxMOVEM_RM_Pseudo<MxType8d, MxType8.JOp>;
def MOVM16mj_P : MxMOVEM_RM_Pseudo<MxType16r, MxType16.JOp>;
def MOVM32mj_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.JOp>;
-def MOVM8mp_P : MxMOVEM_RM_Pseudo<MxType8d, MxType8.POp>;
def MOVM16mp_P : MxMOVEM_RM_Pseudo<MxType16r, MxType16.POp>;
def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 23c5c76a47479b..a6e3c155e8a6cb 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -542,7 +542,6 @@ bool M68kInstrInfo::ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const {
bool M68kInstrInfo::ExpandMOVEM(MachineInstrBuilder &MIB,
const MCInstrDesc &Desc, bool IsRM) const {
int Reg = 0, Offset = 0, Base = 0;
- auto XR32 = RI.getRegClass(M68k::XR32RegClassID);
auto DL = MIB->getDebugLoc();
auto MI = MIB.getInstr();
auto &MBB = *MIB->getParent();
@@ -557,13 +556,6 @@ bool M68kInstrInfo::ExpandMOVEM(MachineInstrBuilder &MIB,
Reg = MIB->getOperand(2).getReg();
}
- // If the register is not in XR32 then it is smaller than 32 bit, we
- // implicitly promote it to 32
- if (!XR32->contains(Reg)) {
- Reg = RI.getMatchingMegaReg(Reg, XR32);
- assert(Reg && "Has not meaningful MEGA register");
- }
-
unsigned Mask = 1 << RI.getSpillRegisterOrder(Reg);
if (IsRM) {
BuildMI(MBB, MI, DL, Desc)
@@ -734,22 +726,24 @@ namespace {
unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI,
const M68kSubtarget &STI, bool load) {
- switch (TRI->getRegSizeInBits(*RC)) {
+ switch (TRI->getSpillSize(*RC)) {
default:
+ LLVM_DEBUG(dbgs() << "Cannot determine appropriate opcode for load/store to/from "
+ << TRI->getName(Reg) << " of class " << TRI->getRegClassName(RC)
+ << " with spill size " << TRI->getSpillSize(*RC) << '\n');
llvm_unreachable("Unknown spill size");
- case 8:
+ case 2:
+ if (M68k::XR16RegClass.hasSubClassEq(RC))
+ return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
if (M68k::DR8RegClass.hasSubClassEq(RC))
- return load ? M68k::MOV8dp : M68k::MOV8pd;
+ return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
if (M68k::CCRCRegClass.hasSubClassEq(RC))
- return load ? M68k::MOV16cp : M68k::MOV16pc;
-
- llvm_unreachable("Unknown 1-byte regclass");
- case 16:
- assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
- return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
- case 32:
- assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass");
- return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;
+ return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
+ llvm_unreachable("Unknown 2-byte regclass");
+ case 4:
+ if (M68k::XR32RegClass.hasSubClassEq(RC))
+ return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;
+ llvm_unreachable("Unknown 4-byte regclass");
}
}
diff --git a/llvm/lib/Target/M68k/M68kRegisterInfo.td b/llvm/lib/Target/M68k/M68kRegisterInfo.td
index 45b492eba4ec07..f0f70b4aab3c0a 100644
--- a/llvm/lib/Target/M68k/M68kRegisterInfo.td
+++ b/llvm/lib/Target/M68k/M68kRegisterInfo.td
@@ -99,52 +99,78 @@ class MxRegClass<list<ValueType> regTypes, int alignment, dag regList>
: RegisterClass<"M68k", regTypes, alignment, regList>;
// Data Registers
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<8,16,16>]> in
def DR8 : MxRegClass<[i8], 16, (sequence "BD%u", 0, 7)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
def DR16 : MxRegClass<[i16], 16, (sequence "WD%u", 0, 7)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def DR32 : MxRegClass<[i32], 32, (sequence "D%u", 0, 7)>;
// Address Registers
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
def AR16 : MxRegClass<[i16], 16, (add (sequence "WA%u", 0, 6), WSP)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def AR32 : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6), SP)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def AR32_NOSP : MxRegClass<[i32], 32, (sequence "A%u", 0, 6)>;
// Index Register Classes
// FIXME try alternative ordering like `D0, D1, A0, A1, ...`
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
def XR16 : MxRegClass<[i16], 16, (add DR16, AR16)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def XR32 : MxRegClass<[i32], 32, (add DR32, AR32)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def SPC : MxRegClass<[i32], 32, (add SP)>;
// Floating Point Data Registers
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def FPDR32 : MxRegClass<[f32], 32, (sequence "FP%u", 0, 7)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<64,64,32>]> in
def FPDR64 : MxRegClass<[f64], 32, (add FPDR32)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<80,128,32>]> in
def FPDR80 : MxRegClass<[f80], 32, (add FPDR32)>;
let CopyCost = -1 in {
+ let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<8,16,16>]> in
def CCRC : MxRegClass<[i8], 16, (add CCR)>;
+ let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
def SRC : MxRegClass<[i16], 16, (add SR)>;
// Float Point System Control Registers
+ let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def FPIC : MxRegClass<[i32], 32, (add FPIAR)>;
+ let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def FPCSC : MxRegClass<[i32], 32, (add FPC, FPS)>;
+ let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def FPSYSC : MxRegClass<[i32], 32, (add FPCSC, FPIC)>;
}
let isAllocatable = 0 in {
+ let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def PCC : MxRegClass<[i32], 32, (add PC)>;
}
// Register used with tail call
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
def DR16_TC : MxRegClass<[i16], 16, (add D0, D1)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def DR32_TC : MxRegClass<[i32], 32, (add D0, D1)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
def AR16_TC : MxRegClass<[i16], 16, (add A0, A1)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def AR32_TC : MxRegClass<[i32], 32, (add A0, A1)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<16,16,16>]> in
def XR16_TC : MxRegClass<[i16], 16, (add DR16_TC, AR16_TC)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def XR32_TC : MxRegClass<[i32], 32, (add DR32_TC, AR32_TC)>;
// These classes provide spill/restore order if used with MOVEM instruction
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def SPILL : MxRegClass<[i32], 32, (add XR32)>;
+let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<32,32,32>]> in
def SPILL_R : MxRegClass<[i32], 32, (add SP, (sequence "A%u", 6, 0), (sequence "D%u", 7, 0))>;
diff --git a/llvm/test/CodeGen/M68k/PR57660.ll b/llvm/test/CodeGen/M68k/PR57660.ll
index bad949b08cafac..359f0c24963568 100644
--- a/llvm/test/CodeGen/M68k/PR57660.ll
+++ b/llvm/test/CodeGen/M68k/PR57660.ll
@@ -8,10 +8,10 @@ define dso_local void @foo1() {
; CHECK-NEXT: suba.l #2, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -6
; CHECK-NEXT: moveq #0, %d0
-; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: movem.w %d0, (0,%sp)
; CHECK-NEXT: .LBB0_1: ; %do.body
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT: movem.w (0,%sp), %d0
; CHECK-NEXT: cmpi.b #0, %d0
; CHECK-NEXT: bne .LBB0_1
; CHECK-NEXT: ; %bb.2: ; %do.end
@@ -39,24 +39,24 @@ define i32 @foo2(ptr noundef %0) {
; CHECK-NEXT: .cfi_def_cfa_offset -8
; CHECK-NEXT: move.l (8,%sp), %a0
; CHECK-NEXT: move.b (%a0), %d0
-; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: movem.w %d0, (0,%sp)
; CHECK-NEXT: and.b #1, %d0
-; CHECK-NEXT: move.b %d0, (2,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: movem.w %d0, (2,%sp)
; CHECK-NEXT: sub.b #1, %d0
; CHECK-NEXT: bgt .LBB1_2
; CHECK-NEXT: ; %bb.1: ; %if
-; CHECK-NEXT: move.b (2,%sp), %d0 ; 1-byte Folded Reload
-; CHECK-NEXT: move.b (0,%sp), %d1 ; 1-byte Folded Reload
+; CHECK-NEXT: movem.w (2,%sp), %d0
+; CHECK-NEXT: movem.w (0,%sp), %d1
; CHECK-NEXT: add.b %d1, %d0
; CHECK-NEXT: bra .LBB1_3
; CHECK-NEXT: .LBB1_2: ; %else
-; CHECK-NEXT: move.b (2,%sp), %d1 ; 1-byte Folded Reload
-; CHECK-NEXT: move.b (0,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT: movem.w (2,%sp), %d1
+; CHECK-NEXT: movem.w (0,%sp), %d0
; CHECK-NEXT: sub.b %d1, %d0
-; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill
+; CHECK-NEXT: movem.w %d0, (0,%sp)
; CHECK-NEXT: .LBB1_3: ; %cont
-; CHECK-NEXT: move.b %d0, (2,%sp) ; 1-byte Folded Spill
-; CHECK-NEXT: move.b (2,%sp), %d0 ; 1-byte Folded Reload
+; CHECK-NEXT: movem.w %d0, (2,%sp)
+; CHECK-NEXT: movem.w (2,%sp), %d0
; CHECK-NEXT: ext.w %d0
; CHECK-NEXT: ext.l %d0
; CHECK-NEXT: adda.l #4, %sp
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