[llvm] [ARM][Codegen] Fix vector data miscompilation in arm32be (PR #105519)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 30 02:35:26 PDT 2024
https://github.com/Zhenhang1213 updated https://github.com/llvm/llvm-project/pull/105519
>From ba395a7bfb56855ceae727eae68e353d9d35aa81 Mon Sep 17 00:00:00 2001
From: Austin <zhenhangwang at huawei.com>
Date: Mon, 26 Aug 2024 10:11:04 +0800
Subject: [PATCH 1/3] [ARM][Codegen] Fix vector data miscompilation in arm32be
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
.../ARM/big-endian-neon-fp16-bitconv.ll | 3 +-
llvm/test/CodeGen/ARM/big-endian-vmov.ll | 1 -
llvm/test/CodeGen/Thumb2/mve-be.ll | 2 -
llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll | 2 -
.../test/CodeGen/Thumb2/mve-pred-loadstore.ll | 8 +---
llvm/test/CodeGen/Thumb2/mve-pred-spill.ll | 18 ++++-----
llvm/test/CodeGen/Thumb2/mve-vmovimm.ll | 37 +++++++------------
8 files changed, 26 insertions(+), 47 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 4ab0433069ae66..568aa210e116ed 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -7966,7 +7966,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
if (Val.getNode()) {
SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
- return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
+ return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Vmov);
}
// Try an immediate VMVN.
diff --git a/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll b/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
index 4026495a0f2b41..a4f5d1c61eae73 100644
--- a/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
@@ -101,9 +101,8 @@ define void @conv_v4i16_to_v4f16( <4 x i16> %a, ptr %store ) {
; CHECK-NEXT: vmov.i64 d16, #0xffff00000000ffff
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vrev64.16 d18, d0
-; CHECK-NEXT: vrev64.16 d17, d17
-; CHECK-NEXT: vrev64.16 d16, d16
; CHECK-NEXT: vadd.i16 d16, d18, d16
+; CHECK-NEXT: vrev64.16 d17, d17
; CHECK-NEXT: vadd.f16 d16, d16, d17
; CHECK-NEXT: vrev64.16 d16, d16
; CHECK-NEXT: vstr d16, [r0]
diff --git a/llvm/test/CodeGen/ARM/big-endian-vmov.ll b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
index 1cb7a030d58c26..3f372905a6e43b 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vmov.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
@@ -177,7 +177,6 @@ define arm_aapcs_vfpcc <4 x i32> @and_v4i32_b(<4 x i32> %a) {
; CHECK-BE: @ %bb.0:
; CHECK-BE-NEXT: vmov.i64 q8, #0xffff00ff0000ff
; CHECK-BE-NEXT: vrev64.32 q9, q0
-; CHECK-BE-NEXT: vrev64.32 q8, q8
; CHECK-BE-NEXT: vand q8, q9, q8
; CHECK-BE-NEXT: vrev64.32 q0, q8
; CHECK-BE-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-be.ll b/llvm/test/CodeGen/Thumb2/mve-be.ll
index 2f2ecc76472374..e1db733b13b415 100644
--- a/llvm/test/CodeGen/Thumb2/mve-be.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-be.ll
@@ -232,7 +232,6 @@ define arm_aapcs_vfpcc <16 x i8> @and_v16i8_le(<4 x i32> %src) {
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vrev64.8 q1, q0
; CHECK-BE-NEXT: vmov.i32 q0, #0x1
-; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vand q1, q1, q0
; CHECK-BE-NEXT: vrev64.8 q0, q1
; CHECK-BE-NEXT: bx lr
@@ -254,7 +253,6 @@ define arm_aapcs_vfpcc <16 x i8> @and_v16i8_be(<4 x i32> %src) {
; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vrev64.8 q1, q0
; CHECK-BE-NEXT: vmov.i32 q0, #0x1000000
-; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vand q1, q1, q0
; CHECK-BE-NEXT: vrev64.8 q0, q1
; CHECK-BE-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
index 470007878ec842..0d0e45956080de 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
@@ -115,7 +115,6 @@ define arm_aapcs_vfpcc <8 x i16> @bitcast_to_v8i1(i8 %b, <8 x i16> %a) {
; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr
; CHECK-BE-NEXT: vrev64.16 q1, q0
; CHECK-BE-NEXT: vmov.i32 q0, #0x0
-; CHECK-BE-NEXT: vrev32.16 q0, q0
; CHECK-BE-NEXT: vpsel q1, q1, q0
; CHECK-BE-NEXT: vrev64.16 q0, q1
; CHECK-BE-NEXT: add sp, #4
@@ -145,7 +144,6 @@ define arm_aapcs_vfpcc <16 x i8> @bitcast_to_v16i1(i16 %b, <16 x i8> %a) {
; CHECK-BE-NEXT: vrev64.8 q1, q0
; CHECK-BE-NEXT: rbit r0, r0
; CHECK-BE-NEXT: vmov.i32 q0, #0x0
-; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: lsrs r0, r0, #16
; CHECK-BE-NEXT: vmsr p0, r0
; CHECK-BE-NEXT: vpsel q1, q1, q0
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
index a92adf6f1a067b..ba3d5c22fc671b 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll
@@ -105,7 +105,6 @@ define arm_aapcs_vfpcc <8 x i16> @load_v8i1(ptr %src, <8 x i16> %a) {
; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr
; CHECK-BE-NEXT: vrev64.16 q1, q0
; CHECK-BE-NEXT: vmov.i32 q0, #0x0
-; CHECK-BE-NEXT: vrev32.16 q0, q0
; CHECK-BE-NEXT: vpsel q1, q1, q0
; CHECK-BE-NEXT: vrev64.16 q0, q1
; CHECK-BE-NEXT: bx lr
@@ -130,7 +129,6 @@ define arm_aapcs_vfpcc <16 x i8> @load_v16i1(ptr %src, <16 x i8> %a) {
; CHECK-BE-NEXT: vrev64.8 q1, q0
; CHECK-BE-NEXT: vmov.i32 q0, #0x0
; CHECK-BE-NEXT: rbit r0, r0
-; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: lsrs r0, r0, #16
; CHECK-BE-NEXT: vmsr p0, r0
; CHECK-BE-NEXT: vpsel q1, q1, q0
@@ -416,10 +414,9 @@ define arm_aapcs_vfpcc <8 x i16> @load_predcast8(ptr %i, <8 x i16> %a) {
;
; CHECK-BE-LABEL: load_predcast8:
; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: vldr p0, [r0]
; CHECK-BE-NEXT: vrev64.16 q1, q0
; CHECK-BE-NEXT: vmov.i32 q0, #0x0
-; CHECK-BE-NEXT: vldr p0, [r0]
-; CHECK-BE-NEXT: vrev32.16 q0, q0
; CHECK-BE-NEXT: vpsel q1, q1, q0
; CHECK-BE-NEXT: vrev64.16 q0, q1
; CHECK-BE-NEXT: bx lr
@@ -439,10 +436,9 @@ define arm_aapcs_vfpcc <16 x i8> @load_predcast16(ptr %i, <16 x i8> %a) {
;
; CHECK-BE-LABEL: load_predcast16:
; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: vldr p0, [r0]
; CHECK-BE-NEXT: vrev64.8 q1, q0
; CHECK-BE-NEXT: vmov.i32 q0, #0x0
-; CHECK-BE-NEXT: vldr p0, [r0]
-; CHECK-BE-NEXT: vrev32.8 q0, q0
; CHECK-BE-NEXT: vpsel q1, q1, q0
; CHECK-BE-NEXT: vrev64.8 q0, q1
; CHECK-BE-NEXT: bx lr
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll b/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
index 3bc129d0fd92e5..c17066126083a9 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
@@ -156,11 +156,10 @@ define arm_aapcs_vfpcc <8 x i16> @shuffle1_v8i16(<8 x i16> %src, <8 x i16> %a) {
; CHECK-BE-NEXT: .pad #8
; CHECK-BE-NEXT: sub sp, #8
; CHECK-BE-NEXT: vrev64.16 q4, q1
-; CHECK-BE-NEXT: vmov.i32 q1, #0x0
-; CHECK-BE-NEXT: vrev64.16 q2, q0
-; CHECK-BE-NEXT: vrev32.16 q1, q1
-; CHECK-BE-NEXT: vcmp.i16 eq, q2, zr
-; CHECK-BE-NEXT: vpsel q1, q4, q1
+; CHECK-BE-NEXT: vrev64.16 q1, q0
+; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr
+; CHECK-BE-NEXT: vmov.i32 q0, #0x0
+; CHECK-BE-NEXT: vpsel q1, q4, q0
; CHECK-BE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
; CHECK-BE-NEXT: vrev64.16 q0, q1
; CHECK-BE-NEXT: bl ext_i16
@@ -209,11 +208,10 @@ define arm_aapcs_vfpcc <16 x i8> @shuffle1_v16i8(<16 x i8> %src, <16 x i8> %a) {
; CHECK-BE-NEXT: .pad #8
; CHECK-BE-NEXT: sub sp, #8
; CHECK-BE-NEXT: vrev64.8 q4, q1
-; CHECK-BE-NEXT: vmov.i32 q1, #0x0
-; CHECK-BE-NEXT: vrev64.8 q2, q0
-; CHECK-BE-NEXT: vrev32.8 q1, q1
-; CHECK-BE-NEXT: vcmp.i8 eq, q2, zr
-; CHECK-BE-NEXT: vpsel q1, q4, q1
+; CHECK-BE-NEXT: vrev64.8 q1, q0
+; CHECK-BE-NEXT: vcmp.i8 eq, q1, zr
+; CHECK-BE-NEXT: vmov.i32 q0, #0x0
+; CHECK-BE-NEXT: vpsel q1, q4, q0
; CHECK-BE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
; CHECK-BE-NEXT: vrev64.8 q0, q1
; CHECK-BE-NEXT: bl ext_i8
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
index 729e4c5e89c75e..868b23b6805649 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
@@ -127,7 +127,6 @@ define arm_aapcs_vfpcc <16 x i8> @xor_int8_32(<16 x i8> %a) {
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i32 q1, #0x1
; CHECKBE-NEXT: vrev64.8 q2, q0
-; CHECKBE-NEXT: vrev32.8 q1, q1
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
@@ -160,9 +159,8 @@ define arm_aapcs_vfpcc <16 x i8> @xor_int8_64(<16 x i8> %a) {
; CHECKBE-LABEL: xor_int8_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff0000ffff00ffff
-; CHECKBE-NEXT: vrev64.8 q2, q1
-; CHECKBE-NEXT: vrev64.8 q1, q0
-; CHECKBE-NEXT: veor q1, q1, q2
+; CHECKBE-NEXT: vrev64.8 q2, q0
+; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
@@ -372,9 +370,8 @@ define arm_aapcs_vfpcc <8 x i16> @xor_int16_64(<8 x i16> %a) {
; CHECKBE-LABEL: xor_int16_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff0000000000ff
-; CHECKBE-NEXT: vrev64.16 q2, q1
-; CHECKBE-NEXT: vrev64.16 q1, q0
-; CHECKBE-NEXT: veor q1, q1, q2
+; CHECKBE-NEXT: vrev64.16 q2, q0
+; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
@@ -756,9 +753,8 @@ define arm_aapcs_vfpcc <4 x i32> @xor_int32_64(<4 x i32> %a) {
; CHECKBE-LABEL: xor_int32_64:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff00ff0000ff00ff
-; CHECKBE-NEXT: vrev64.32 q2, q1
-; CHECKBE-NEXT: vrev64.32 q1, q0
-; CHECKBE-NEXT: veor q1, q1, q2
+; CHECKBE-NEXT: vrev64.32 q2, q0
+; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
; CHECKBE-NEXT: bx lr
entry:
@@ -985,9 +981,8 @@ define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f000f0f(<16 x i8> %a) {
; CHECKBE-LABEL: xor_int64_0f000f0f:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff00ff000000ff00
-; CHECKBE-NEXT: vrev64.8 q2, q1
-; CHECKBE-NEXT: vrev64.8 q1, q0
-; CHECKBE-NEXT: veor q1, q1, q2
+; CHECKBE-NEXT: vrev64.8 q2, q0
+; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
@@ -1019,9 +1014,8 @@ define arm_aapcs_vfpcc <8 x i16> @xor_int64_ff00ffff(<8 x i16> %a) {
; CHECKBE-LABEL: xor_int64_ff00ffff:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xffff0000ffffffff
-; CHECKBE-NEXT: vrev64.16 q2, q1
-; CHECKBE-NEXT: vrev64.16 q1, q0
-; CHECKBE-NEXT: veor q1, q1, q2
+; CHECKBE-NEXT: vrev64.16 q2, q0
+; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
@@ -1055,7 +1049,6 @@ define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f0f0f0f0f0f0f0f(<16 x i8> %a) {
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i16 q1, #0xff
; CHECKBE-NEXT: vrev64.8 q2, q0
-; CHECKBE-NEXT: vrev16.8 q1, q1
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
@@ -1196,9 +1189,8 @@ define arm_aapcs_vfpcc <16 x i8> @test(<16 x i8> %i) {
; CHECKBE-LABEL: test:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xff00ff000000ff00
-; CHECKBE-NEXT: vrev64.8 q2, q1
-; CHECKBE-NEXT: vrev64.8 q1, q0
-; CHECKBE-NEXT: vorr q1, q1, q2
+; CHECKBE-NEXT: vrev64.8 q2, q0
+; CHECKBE-NEXT: vorr q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
; CHECKBE-NEXT: bx lr
entry:
@@ -1216,9 +1208,8 @@ define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) {
; CHECKBE-LABEL: test2:
; CHECKBE: @ %bb.0: @ %entry
; CHECKBE-NEXT: vmov.i64 q1, #0xffff0000ffffffff
-; CHECKBE-NEXT: vrev64.16 q2, q1
-; CHECKBE-NEXT: vrev64.16 q1, q0
-; CHECKBE-NEXT: vorr q1, q1, q2
+; CHECKBE-NEXT: vrev64.16 q2, q0
+; CHECKBE-NEXT: vorr q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
; CHECKBE-NEXT: bx lr
entry:
>From 1a0d93806b31a872da1154beea6e01fb024a573c Mon Sep 17 00:00:00 2001
From: Austin <zhenhangwang at huawei.com>
Date: Mon, 26 Aug 2024 10:17:48 +0800
Subject: [PATCH 2/3] [Clang][Codegen] fix vector data by modifying VMVN
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
llvm/test/CodeGen/ARM/big-endian-vmov.ll | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 568aa210e116ed..d627544dcca85b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -7976,7 +7976,7 @@ SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
VT, ST->hasMVEIntegerOps() ? MVEVMVNModImm : VMVNModImm);
if (Val.getNode()) {
SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
- return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
+ return DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, VT, Vmov);
}
// Use vmov.f32 to materialize other v2f32 and v4f32 splats.
diff --git a/llvm/test/CodeGen/ARM/big-endian-vmov.ll b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
index 3f372905a6e43b..8a4532a2ae2d1b 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vmov.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
@@ -226,7 +226,6 @@ define arm_aapcs_vfpcc <8 x i16> @xor_v8i16_m1(<8 x i16> %a) {
; CHECK-BE: @ %bb.0:
; CHECK-BE-NEXT: vmvn.i32 q8, #0x10000
; CHECK-BE-NEXT: vrev64.16 q9, q0
-; CHECK-BE-NEXT: vrev32.16 q8, q8
; CHECK-BE-NEXT: veor q8, q9, q8
; CHECK-BE-NEXT: vrev64.16 q0, q8
; CHECK-BE-NEXT: bx lr
>From 70052abf3bb8a1b6cbe84b0a772fc999c0668c76 Mon Sep 17 00:00:00 2001
From: Austin <zhenhangwang at huawei.com>
Date: Tue, 27 Aug 2024 09:48:01 +0800
Subject: [PATCH 3/3] fix rearranged i64 vectors in PerformBITCASTCombine and
remove the FIXME in tests
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 13 --
llvm/test/CodeGen/ARM/big-endian-vmov.ll | 32 ++--
llvm/test/CodeGen/ARM/vmov.ll | 177 ++++++++++++-----------
llvm/test/CodeGen/Thumb2/mve-vmovimm.ll | 29 ++--
4 files changed, 129 insertions(+), 122 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d627544dcca85b..60732d9c85bc5f 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -7121,19 +7121,6 @@ static SDValue isVMOVModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
ImmMask <<= 1;
}
- if (DAG.getDataLayout().isBigEndian()) {
- // Reverse the order of elements within the vector.
- unsigned BytesPerElem = VectorVT.getScalarSizeInBits() / 8;
- unsigned Mask = (1 << BytesPerElem) - 1;
- unsigned NumElems = 8 / BytesPerElem;
- unsigned NewImm = 0;
- for (unsigned ElemNum = 0; ElemNum < NumElems; ++ElemNum) {
- unsigned Elem = ((Imm >> ElemNum * BytesPerElem) & Mask);
- NewImm |= Elem << (NumElems - ElemNum - 1) * BytesPerElem;
- }
- Imm = NewImm;
- }
-
// Op=1, Cmode=1110.
OpCmode = 0x1e;
VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
diff --git a/llvm/test/CodeGen/ARM/big-endian-vmov.ll b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
index 8a4532a2ae2d1b..1c846a347c704c 100644
--- a/llvm/test/CodeGen/ARM/big-endian-vmov.ll
+++ b/llvm/test/CodeGen/ARM/big-endian-vmov.ll
@@ -128,10 +128,15 @@ define arm_aapcs_vfpcc <1 x i64> @vmov_i64_a() {
}
define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
-; CHECK-LABEL: vmov_i64_b:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov.i64 d0, #0xffff00ff0000ff
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: vmov_i64_b:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: vmov.i64 d0, #0xffff00ff0000ff
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: vmov_i64_b:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: vmov.i64 d0, #0xff0000ff00ffff00
+; CHECK-BE-NEXT: bx lr
ret <1 x i64> <i64 72056498804490495>
}
@@ -157,11 +162,17 @@ define arm_aapcs_vfpcc <4 x i32> @vmov_v4i32_b() {
}
define arm_aapcs_vfpcc <2 x i64> @and_v2i64_b(<2 x i64> %a) {
-; CHECK-LABEL: and_v2i64_b:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov.i64 q8, #0xffff00ff0000ff
-; CHECK-NEXT: vand q0, q0, q8
-; CHECK-NEXT: bx lr
+; CHECK-LE-LABEL: and_v2i64_b:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: vmov.i64 q8, #0xffff00ff0000ff
+; CHECK-LE-NEXT: vand q0, q0, q8
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: and_v2i64_b:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00
+; CHECK-BE-NEXT: vand q0, q0, q8
+; CHECK-BE-NEXT: bx lr
%b = and <2 x i64> %a, <i64 72056498804490495, i64 72056498804490495>
ret <2 x i64> %b
}
@@ -175,7 +186,7 @@ define arm_aapcs_vfpcc <4 x i32> @and_v4i32_b(<4 x i32> %a) {
;
; CHECK-BE-LABEL: and_v4i32_b:
; CHECK-BE: @ %bb.0:
-; CHECK-BE-NEXT: vmov.i64 q8, #0xffff00ff0000ff
+; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00
; CHECK-BE-NEXT: vrev64.32 q9, q0
; CHECK-BE-NEXT: vand q8, q9, q8
; CHECK-BE-NEXT: vrev64.32 q0, q8
@@ -197,7 +208,6 @@ define arm_aapcs_vfpcc <8 x i16> @vmvn_v16i8_m1() {
ret <8 x i16> <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
}
-; FIXME: This is incorrect for BE
define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
; CHECK-LE-LABEL: and_v8i16_m1:
; CHECK-LE: @ %bb.0:
diff --git a/llvm/test/CodeGen/ARM/vmov.ll b/llvm/test/CodeGen/ARM/vmov.ll
index 8835497669b324..73d90e95be67c0 100644
--- a/llvm/test/CodeGen/ARM/vmov.ll
+++ b/llvm/test/CodeGen/ARM/vmov.ll
@@ -7,7 +7,7 @@ define arm_aapcs_vfpcc <8 x i8> @v_movi8() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 d0, #0x8
; CHECK-NEXT: mov pc, lr
- ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define arm_aapcs_vfpcc <4 x i16> @v_movi16a() nounwind {
@@ -15,7 +15,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_movi16a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d0, #0x10
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
+ ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
}
define arm_aapcs_vfpcc <4 x i16> @v_movi16b() nounwind {
@@ -23,7 +23,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_movi16b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 d0, #0x1000
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
+ ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
}
define arm_aapcs_vfpcc <4 x i16> @v_mvni16a() nounwind {
@@ -31,7 +31,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_mvni16a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d0, #0x10
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
+ ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
}
define arm_aapcs_vfpcc <4 x i16> @v_mvni16b() nounwind {
@@ -39,7 +39,7 @@ define arm_aapcs_vfpcc <4 x i16> @v_mvni16b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i16 d0, #0x1000
; CHECK-NEXT: mov pc, lr
- ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
+ ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32a() nounwind {
@@ -47,7 +47,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 32, i32 32 >
+ ret <2 x i32> < i32 32, i32 32 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32b() nounwind {
@@ -55,7 +55,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x2000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 8192, i32 8192 >
+ ret <2 x i32> < i32 8192, i32 8192 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32c() nounwind {
@@ -63,7 +63,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32c() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x200000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 2097152, i32 2097152 >
+ ret <2 x i32> < i32 2097152, i32 2097152 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32d() nounwind {
@@ -71,7 +71,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32d() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20000000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 536870912, i32 536870912 >
+ ret <2 x i32> < i32 536870912, i32 536870912 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32e() nounwind {
@@ -79,7 +79,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32e() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20ff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 8447, i32 8447 >
+ ret <2 x i32> < i32 8447, i32 8447 >
}
define arm_aapcs_vfpcc <2 x i32> @v_movi32f() nounwind {
@@ -87,7 +87,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_movi32f() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 d0, #0x20ffff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 2162687, i32 2162687 >
+ ret <2 x i32> < i32 2162687, i32 2162687 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32a() nounwind {
@@ -95,7 +95,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4294967263, i32 4294967263 >
+ ret <2 x i32> < i32 4294967263, i32 4294967263 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32b() nounwind {
@@ -103,7 +103,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x2000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4294959103, i32 4294959103 >
+ ret <2 x i32> < i32 4294959103, i32 4294959103 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32c() nounwind {
@@ -111,7 +111,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32c() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x200000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4292870143, i32 4292870143 >
+ ret <2 x i32> < i32 4292870143, i32 4292870143 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32d() nounwind {
@@ -119,7 +119,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32d() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20000000
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 3758096383, i32 3758096383 >
+ ret <2 x i32> < i32 3758096383, i32 3758096383 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32e() nounwind {
@@ -127,7 +127,7 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32e() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20ff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4294958848, i32 4294958848 >
+ ret <2 x i32> < i32 4294958848, i32 4294958848 >
}
define arm_aapcs_vfpcc <2 x i32> @v_mvni32f() nounwind {
@@ -135,15 +135,20 @@ define arm_aapcs_vfpcc <2 x i32> @v_mvni32f() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmvn.i32 d0, #0x20ffff
; CHECK-NEXT: mov pc, lr
- ret <2 x i32> < i32 4292804608, i32 4292804608 >
+ ret <2 x i32> < i32 4292804608, i32 4292804608 >
}
define arm_aapcs_vfpcc <1 x i64> @v_movi64() nounwind {
-; CHECK-LABEL: v_movi64:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmov.i64 d0, #0xff0000ff0000ffff
-; CHECK-NEXT: mov pc, lr
- ret <1 x i64> < i64 18374687574888349695 >
+; CHECK-LE-LABEL: v_movi64:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: vmov.i64 d0, #0xff0000ff0000ffff
+; CHECK-LE-NEXT: mov pc, lr
+;
+; CHECK-BE-LABEL: v_movi64:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: vmov.i64 d0, #0xffffff0000ff
+; CHECK-BE-NEXT: mov pc, lr
+ ret <1 x i64> < i64 18374687574888349695 >
}
define arm_aapcs_vfpcc <16 x i8> @v_movQi8() nounwind {
@@ -151,7 +156,7 @@ define arm_aapcs_vfpcc <16 x i8> @v_movQi8() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i8 q0, #0x8
; CHECK-NEXT: mov pc, lr
- ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+ ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define arm_aapcs_vfpcc <8 x i16> @v_movQi16a() nounwind {
@@ -159,7 +164,7 @@ define arm_aapcs_vfpcc <8 x i16> @v_movQi16a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q0, #0x10
; CHECK-NEXT: mov pc, lr
- ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
+ ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
define arm_aapcs_vfpcc <8 x i16> @v_movQi16b() nounwind {
@@ -167,7 +172,7 @@ define arm_aapcs_vfpcc <8 x i16> @v_movQi16b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i16 q0, #0x1000
; CHECK-NEXT: mov pc, lr
- ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
+ ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32a() nounwind {
@@ -175,7 +180,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32a() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
+ ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32b() nounwind {
@@ -183,7 +188,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32b() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x2000
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
+ ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32c() nounwind {
@@ -191,7 +196,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32c() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x200000
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
+ ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32d() nounwind {
@@ -199,7 +204,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32d() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20000000
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
+ ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32e() nounwind {
@@ -207,7 +212,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32e() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20ff
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
+ ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
}
define arm_aapcs_vfpcc <4 x i32> @v_movQi32f() nounwind {
@@ -215,7 +220,7 @@ define arm_aapcs_vfpcc <4 x i32> @v_movQi32f() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i32 q0, #0x20ffff
; CHECK-NEXT: mov pc, lr
- ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
+ ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
}
define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind {
@@ -223,7 +228,7 @@ define arm_aapcs_vfpcc <2 x i64> @v_movQi64() nounwind {
; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.i64 q0, #0xff0000ff0000ffff
; CHECK-NEXT: mov pc, lr
- ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
+ ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
}
; Check for correct assembler printing for immediate values.
@@ -265,9 +270,9 @@ define arm_aapcs_vfpcc <8 x i16> @vmovls8(ptr %A) nounwind {
; CHECK-BE-NEXT: vmovl.s8 q8, d16
; CHECK-BE-NEXT: vrev64.16 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
- ret <8 x i16> %tmp2
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
+ ret <8 x i16> %tmp2
}
define arm_aapcs_vfpcc <4 x i32> @vmovls16(ptr %A) nounwind {
@@ -283,9 +288,9 @@ define arm_aapcs_vfpcc <4 x i32> @vmovls16(ptr %A) nounwind {
; CHECK-BE-NEXT: vmovl.s16 q8, d16
; CHECK-BE-NEXT: vrev64.32 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, ptr %A
- %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
- ret <4 x i32> %tmp2
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
+ ret <4 x i32> %tmp2
}
define arm_aapcs_vfpcc <2 x i64> @vmovls32(ptr %A) nounwind {
@@ -294,9 +299,9 @@ define arm_aapcs_vfpcc <2 x i64> @vmovls32(ptr %A) nounwind {
; CHECK-NEXT: vld1.32 {d16}, [r0:64]
; CHECK-NEXT: vmovl.s32 q0, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, ptr %A
- %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
- ret <2 x i64> %tmp2
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
+ ret <2 x i64> %tmp2
}
define arm_aapcs_vfpcc <8 x i16> @vmovlu8(ptr %A) nounwind {
@@ -312,9 +317,9 @@ define arm_aapcs_vfpcc <8 x i16> @vmovlu8(ptr %A) nounwind {
; CHECK-BE-NEXT: vmovl.u8 q8, d16
; CHECK-BE-NEXT: vrev64.16 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i8>, ptr %A
- %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
- ret <8 x i16> %tmp2
+ %tmp1 = load <8 x i8>, ptr %A
+ %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
+ ret <8 x i16> %tmp2
}
define arm_aapcs_vfpcc <4 x i32> @vmovlu16(ptr %A) nounwind {
@@ -330,9 +335,9 @@ define arm_aapcs_vfpcc <4 x i32> @vmovlu16(ptr %A) nounwind {
; CHECK-BE-NEXT: vmovl.u16 q8, d16
; CHECK-BE-NEXT: vrev64.32 q0, q8
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i16>, ptr %A
- %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
- ret <4 x i32> %tmp2
+ %tmp1 = load <4 x i16>, ptr %A
+ %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
+ ret <4 x i32> %tmp2
}
define arm_aapcs_vfpcc <2 x i64> @vmovlu32(ptr %A) nounwind {
@@ -341,9 +346,9 @@ define arm_aapcs_vfpcc <2 x i64> @vmovlu32(ptr %A) nounwind {
; CHECK-NEXT: vld1.32 {d16}, [r0:64]
; CHECK-NEXT: vmovl.u32 q0, d16
; CHECK-NEXT: mov pc, lr
- %tmp1 = load <2 x i32>, ptr %A
- %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
- ret <2 x i64> %tmp2
+ %tmp1 = load <2 x i32>, ptr %A
+ %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
+ ret <2 x i64> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vmovni16(ptr %A) nounwind {
@@ -360,9 +365,9 @@ define arm_aapcs_vfpcc <8 x i8> @vmovni16(ptr %A) nounwind {
; CHECK-BE-NEXT: vmovn.i16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, ptr %A
- %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
- ret <8 x i8> %tmp2
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vmovni32(ptr %A) nounwind {
@@ -379,9 +384,9 @@ define arm_aapcs_vfpcc <4 x i16> @vmovni32(ptr %A) nounwind {
; CHECK-BE-NEXT: vmovn.i32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, ptr %A
- %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
- ret <4 x i16> %tmp2
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vmovni64(ptr %A) nounwind {
@@ -397,9 +402,9 @@ define arm_aapcs_vfpcc <2 x i32> @vmovni64(ptr %A) nounwind {
; CHECK-BE-NEXT: vmovn.i64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, ptr %A
- %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
- ret <2 x i32> %tmp2
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
+ ret <2 x i32> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vqmovns16(ptr %A) nounwind {
@@ -416,9 +421,9 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovns16(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovn.s16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, ptr %A
- %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
- ret <8 x i8> %tmp2
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vqmovns32(ptr %A) nounwind {
@@ -435,9 +440,9 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovns32(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovn.s32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, ptr %A
- %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
- ret <4 x i16> %tmp2
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vqmovns64(ptr %A) nounwind {
@@ -453,9 +458,9 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovns64(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovn.s64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, ptr %A
- %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
- ret <2 x i32> %tmp2
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(ptr %A) nounwind {
@@ -472,9 +477,9 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovnu16(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovn.u16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, ptr %A
- %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
- ret <8 x i8> %tmp2
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(ptr %A) nounwind {
@@ -491,9 +496,9 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovnu32(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovn.u32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, ptr %A
- %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
- ret <4 x i16> %tmp2
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(ptr %A) nounwind {
@@ -509,9 +514,9 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovnu64(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovn.u64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, ptr %A
- %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
- ret <2 x i32> %tmp2
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
}
define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(ptr %A) nounwind {
@@ -528,9 +533,9 @@ define arm_aapcs_vfpcc <8 x i8> @vqmovuns16(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovun.s16 d16, q8
; CHECK-BE-NEXT: vrev64.8 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <8 x i16>, ptr %A
- %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
- ret <8 x i8> %tmp2
+ %tmp1 = load <8 x i16>, ptr %A
+ %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
+ ret <8 x i8> %tmp2
}
define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(ptr %A) nounwind {
@@ -547,9 +552,9 @@ define arm_aapcs_vfpcc <4 x i16> @vqmovuns32(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovun.s32 d16, q8
; CHECK-BE-NEXT: vrev64.16 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <4 x i32>, ptr %A
- %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
- ret <4 x i16> %tmp2
+ %tmp1 = load <4 x i32>, ptr %A
+ %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
+ ret <4 x i16> %tmp2
}
define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(ptr %A) nounwind {
@@ -565,9 +570,9 @@ define arm_aapcs_vfpcc <2 x i32> @vqmovuns64(ptr %A) nounwind {
; CHECK-BE-NEXT: vqmovun.s64 d16, q8
; CHECK-BE-NEXT: vrev64.32 d0, d16
; CHECK-BE-NEXT: mov pc, lr
- %tmp1 = load <2 x i64>, ptr %A
- %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
- ret <2 x i32> %tmp2
+ %tmp1 = load <2 x i64>, ptr %A
+ %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
+ ret <2 x i32> %tmp2
}
declare <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16>) nounwind readnone
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
index 868b23b6805649..2024abaa3e73f7 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmovimm.ll
@@ -115,7 +115,6 @@ entry:
ret <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
}
-; FIXME: This is incorrect for BE
define arm_aapcs_vfpcc <16 x i8> @xor_int8_32(<16 x i8> %a) {
; CHECKLE-LABEL: xor_int8_32:
; CHECKLE: @ %bb.0: @ %entry
@@ -158,7 +157,7 @@ define arm_aapcs_vfpcc <16 x i8> @xor_int8_64(<16 x i8> %a) {
;
; CHECKBE-LABEL: xor_int8_64:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: vmov.i64 q1, #0xff0000ffff00ffff
+; CHECKBE-NEXT: vmov.i64 q1, #0xffff00ffff0000ff
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
@@ -752,7 +751,7 @@ define arm_aapcs_vfpcc <4 x i32> @xor_int32_64(<4 x i32> %a) {
;
; CHECKBE-LABEL: xor_int32_64:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: vmov.i64 q1, #0xff00ff0000ff00ff
+; CHECKBE-NEXT: vmov.i64 q1, #0xff00ffff00ff00
; CHECKBE-NEXT: vrev64.32 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.32 q0, q1
@@ -882,11 +881,17 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @xor_int64_ff0000ff0000ffff(<2 x i64> %a) {
-; CHECK-LABEL: xor_int64_ff0000ff0000ffff:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i64 q1, #0xff0000ff0000ffff
-; CHECK-NEXT: veor q0, q0, q1
-; CHECK-NEXT: bx lr
+; CHECKLE-LABEL: xor_int64_ff0000ff0000ffff:
+; CHECKLE: @ %bb.0: @ %entry
+; CHECKLE-NEXT: vmov.i64 q1, #0xff0000ff0000ffff
+; CHECKLE-NEXT: veor q0, q0, q1
+; CHECKLE-NEXT: bx lr
+;
+; CHECKBE-LABEL: xor_int64_ff0000ff0000ffff:
+; CHECKBE: @ %bb.0: @ %entry
+; CHECKBE-NEXT: vmov.i64 q1, #0xffffff0000ff
+; CHECKBE-NEXT: veor q0, q0, q1
+; CHECKBE-NEXT: bx lr
entry:
%b = xor <2 x i64> %a, <i64 18374687574888349695, i64 18374687574888349695>
ret <2 x i64> %b
@@ -980,7 +985,7 @@ define arm_aapcs_vfpcc <16 x i8> @xor_int64_0f000f0f(<16 x i8> %a) {
;
; CHECKBE-LABEL: xor_int64_0f000f0f:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: vmov.i64 q1, #0xff00ff000000ff00
+; CHECKBE-NEXT: vmov.i64 q1, #0xff000000ff00ff
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
@@ -1013,7 +1018,7 @@ define arm_aapcs_vfpcc <8 x i16> @xor_int64_ff00ffff(<8 x i16> %a) {
;
; CHECKBE-LABEL: xor_int64_ff00ffff:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: vmov.i64 q1, #0xffff0000ffffffff
+; CHECKBE-NEXT: vmov.i64 q1, #0xffffffff0000ffff
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: veor q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
@@ -1188,7 +1193,7 @@ define arm_aapcs_vfpcc <16 x i8> @test(<16 x i8> %i) {
;
; CHECKBE-LABEL: test:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: vmov.i64 q1, #0xff00ff000000ff00
+; CHECKBE-NEXT: vmov.i64 q1, #0xff000000ff00ff
; CHECKBE-NEXT: vrev64.8 q2, q0
; CHECKBE-NEXT: vorr q1, q2, q1
; CHECKBE-NEXT: vrev64.8 q0, q1
@@ -1207,7 +1212,7 @@ define arm_aapcs_vfpcc <8 x i16> @test2(<8 x i16> %i) {
;
; CHECKBE-LABEL: test2:
; CHECKBE: @ %bb.0: @ %entry
-; CHECKBE-NEXT: vmov.i64 q1, #0xffff0000ffffffff
+; CHECKBE-NEXT: vmov.i64 q1, #0xffffffff0000ffff
; CHECKBE-NEXT: vrev64.16 q2, q0
; CHECKBE-NEXT: vorr q1, q2, q1
; CHECKBE-NEXT: vrev64.16 q0, q1
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