[llvm] [RISCV] Preserve tail agnostic policy in some vector peepholes (PR #105788)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 30 01:26:28 PDT 2024
https://github.com/lukel97 updated https://github.com/llvm/llvm-project/pull/105788
>From 33c3df1f2ff5a9791cd500fba58f932701b92eb3 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Fri, 23 Aug 2024 14:27:12 +0800
Subject: [PATCH 1/2] Precommit tests
---
.../RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll | 12 ++++++++++++
llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 14 ++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll
new file mode 100644
index 00000000000000..6b4d323f8a9e7c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll
@@ -0,0 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
+
+define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %false, <vscale x 1 x i64> %true, i64 %vl) {
+; CHECK-LABEL: undef_passthru:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: ret
+ %v = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %false, <vscale x 1 x i64> %true, <vscale x 1 x i1> splat (i1 true), i64 %vl)
+ ret <vscale x 1 x i64> %v
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index b2526c6df6939e..aa14914b3ef96c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -18,3 +18,17 @@ body: |
%y:gpr = ADDI $x0, 1
%z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */
...
+---
+name: tail_agnostic
+body: |
+ bb.0:
+ liveins: $v8
+ ; CHECK-LABEL: name: tail_agnostic
+ ; CHECK: liveins: $v8
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %passthru:vr = COPY $v8
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+ %passthru:vr = COPY $v8
+ %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+ %y:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 1 /* ta, mu */
+...
>From 7bab2f51db6771e017cba92710e45eda638a7610 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Fri, 23 Aug 2024 14:29:15 +0800
Subject: [PATCH 2/2] [RISCV] Preserve tail agnostic policy in some vector
peepholes
This patch helps avoid regressions in an upcoming patch by making sure we don't accidentally lose a tail agnostic policy when doing some peepholes. There are two places this happens:
1. When converting a vmerge.vvm with an all ones mask to a vmv.v.v, if vmerge's passthru was undefined the tail will always be undef, even if the new passthru (vmerge's old false operand) isn't undef. We can use ta here.
2. When folding a vmv.v.v into its source, if the vmv.v.v had a ta policy we can copy it over, provided that we kept the same VL.
---
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 16 ++++++++++------
.../RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll | 2 +-
.../RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir | 2 +-
llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir | 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 34e5d9224f7150..16f63e54be7f17 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -365,8 +365,10 @@ bool RISCVVectorPeephole::convertVMergeToVMv(MachineInstr &MI) const {
MI.removeOperand(1); // Passthru operand
MI.tieOperands(0, 1); // Tie false to dest
MI.removeOperand(3); // Mask operand
- MI.addOperand(
- MachineOperand::CreateImm(RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED));
+ int64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
+ if (PassthruReg == RISCV::NoRegister)
+ Policy |= RISCVII::TAIL_AGNOSTIC;
+ MI.addOperand(MachineOperand::CreateImm(Policy));
// vmv.v.v doesn't have a mask operand, so we may be able to inflate the
// register class for the destination and passthru operands e.g. VRNoV0 -> VR
@@ -520,10 +522,12 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
*Src->getParent()->getParent()));
}
- // Use a conservative tu,mu policy, RISCVInsertVSETVLI will relax it if
- // passthru is undef.
- Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc()))
- .setImm(RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED);
+ // If MI had a ta policy and the VL didn't increase, we can preserve it.
+ int64_t Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED;
+ if ((MI.getOperand(5).getImm() & RISCVII::TAIL_AGNOSTIC) &&
+ isVLKnownLE(MI.getOperand(3), SrcVL))
+ Policy |= RISCVII::TAIL_AGNOSTIC;
+ Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);
MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
MI.eraseFromParent();
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll
index 6b4d323f8a9e7c..e56bc3aa5c8831 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.ll
@@ -4,7 +4,7 @@
define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %false, <vscale x 1 x i64> %true, i64 %vl) {
; CHECK-LABEL: undef_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
+; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret
%v = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %false, <vscale x 1 x i64> %true, <vscale x 1 x i1> splat (i1 true), i64 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
index 01fff3de0aa8bd..9080fcfb0f0420 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir
@@ -15,7 +15,7 @@ body: |
; CHECK-NEXT: %avl:gprnox0 = COPY $x1
; CHECK-NEXT: %mask:vmv0 = PseudoVMSET_M_B8 %avl, 5 /* e32 */
; CHECK-NEXT: $v0 = COPY %mask
- ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %false, %true, %avl, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %x:vr = PseudoVMV_V_V_M1 %false, %true, %avl, 5 /* e32 */, 1 /* ta, mu */
%false:vr = COPY $v8
%true:vr = COPY $v9
%avl:gprnox0 = COPY $x1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
index aa14914b3ef96c..4294f48a7a2f57 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
@@ -27,7 +27,7 @@ body: |
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %passthru:vr = COPY $v8
- ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 1 /* ta, mu */
%passthru:vr = COPY $v8
%x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
%y:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 1 /* ta, mu */
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