[llvm] [VectorCombine] Add foldShuffleOfIntrinsics. (PR #106502)
Han-Kuan Chen via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 30 01:05:35 PDT 2024
https://github.com/HanKuanChen updated https://github.com/llvm/llvm-project/pull/106502
>From d8f1ab5bb1382d186a1778fe15bd141f970ebac3 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Wed, 28 Aug 2024 23:53:01 -0700
Subject: [PATCH 1/4] [VectorCombine] Pre-commit test.
---
.../VectorCombine/foldShuffleOfIntrinsics.ll | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
diff --git a/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
new file mode 100644
index 00000000000000..ba45f24929c71e
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=vector-combine -S %s | FileCheck %s
+
+define <8 x i32> @test1(<4 x i32> %0, <4 x i32> %1) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP0:%.*]], i1 false)
+; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP1:%.*]], i1 false)
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: ret <8 x i32> [[TMP4]]
+;
+entry:
+ %2 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %0, i1 false)
+ %3 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %1, i1 false)
+ %4 = shufflevector <4 x i32> %2, <4 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i32> %4
+}
+
+define <8 x i32> @test2(<4 x i32> %0, <4 x i32> %1) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP0:%.*]], i1 true)
+; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP1:%.*]], i1 false)
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: ret <8 x i32> [[TMP4]]
+;
+entry:
+ %2 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %0, i1 true)
+ %3 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %1, i1 false)
+ %4 = shufflevector <4 x i32> %2, <4 x i32> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i32> %4
+}
+
+declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
>From 874963226704580f69773745b4356c6227f652d9 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Wed, 28 Aug 2024 23:53:32 -0700
Subject: [PATCH 2/4] [VectorCombine] Add foldShuffleOfIntrinsics.
---
.../Transforms/Vectorize/VectorCombine.cpp | 94 +++++++++++++++++++
.../VectorCombine/foldShuffleOfIntrinsics.ll | 7 +-
2 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 99bd383ab0dead..9ad7276ffb9707 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -115,6 +115,7 @@ class VectorCombine {
bool foldShuffleOfBinops(Instruction &I);
bool foldShuffleOfCastops(Instruction &I);
bool foldShuffleOfShuffles(Instruction &I);
+ bool foldShuffleOfIntrinsics(Instruction &I);
bool foldShuffleToIdentity(Instruction &I);
bool foldShuffleFromReductions(Instruction &I);
bool foldCastFromReductions(Instruction &I);
@@ -1673,6 +1674,98 @@ bool VectorCombine::foldShuffleOfShuffles(Instruction &I) {
return true;
}
+/// Try to convert
+/// "shuffle (intrinsic), (intrinsic)" into "intrinsic (shuffle), (shuffle)".
+bool VectorCombine::foldShuffleOfIntrinsics(Instruction &I) {
+ Value *V0, *V1;
+ ArrayRef<int> OldMask;
+ if (!match(&I, m_Shuffle(m_OneUse(m_Value(V0)), m_OneUse(m_Value(V1)),
+ m_Mask(OldMask))))
+ return false;
+
+ auto *II0 = dyn_cast<IntrinsicInst>(V0);
+ auto *II1 = dyn_cast<IntrinsicInst>(V1);
+ if (!II0 || !II1)
+ return false;
+
+ Intrinsic::ID IID = II0->getIntrinsicID();
+ if (IID != II1->getIntrinsicID())
+ return false;
+
+ auto *ShuffleDstTy = dyn_cast<FixedVectorType>(I.getType());
+ auto *II0Ty = dyn_cast<FixedVectorType>(II0->getType());
+ if (!ShuffleDstTy || !II0Ty)
+ return false;
+
+ switch (IID) {
+ case Intrinsic::abs: {
+ if (cast<Constant>(II0->getArgOperand(1))->isOneValue() !=
+ cast<Constant>(II1->getArgOperand(1))->isOneValue())
+ return false;
+ break;
+ }
+ default:
+ return false;
+ }
+
+ SmallVector<Value *> Args0;
+ SmallVector<Value *> Args1;
+ for (unsigned I = 0; I != II0->arg_size(); ++I) {
+ Args0.push_back(II0->getArgOperand(I));
+ Args1.push_back(II1->getArgOperand(I));
+ }
+ IntrinsicCostAttributes Attr0(IID, II0Ty, Args0);
+ IntrinsicCostAttributes Attr1(IID, II1->getType(), Args1);
+ InstructionCost OldCost =
+ TTI.getIntrinsicInstrCost(Attr0, TTI::TCK_RecipThroughput) +
+ TTI.getIntrinsicInstrCost(Attr1, TTI::TCK_RecipThroughput) +
+ TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, II0Ty, OldMask,
+ TTI::TCK_RecipThroughput, 0, nullptr, {II0, II1}, &I);
+
+ InstructionCost NewCost;
+ switch (IID) {
+ case Intrinsic::abs: {
+ IntrinsicCostAttributes NewAttr(IID, ShuffleDstTy,
+ {ShuffleDstTy, Builder.getInt1Ty()});
+ NewCost = TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, II0Ty,
+ OldMask, TTI::TCK_RecipThroughput) +
+ TTI.getIntrinsicInstrCost(NewAttr, TTI::TCK_RecipThroughput);
+ break;
+ }
+ default:
+ llvm_unreachable("Unexpected intrinsic");
+ }
+
+ LLVM_DEBUG(dbgs() << "Found a shuffle feeding two intrinsics: " << I
+ << "\n OldCost: " << OldCost << " vs NewCost: " << NewCost
+ << "\n");
+
+ if (NewCost > OldCost)
+ return false;
+
+ Value *NewIntrinsic;
+ switch (IID) {
+ case Intrinsic::abs: {
+ Value *Shuf = Builder.CreateShuffleVector(Args0[0], Args1[0], OldMask);
+ NewIntrinsic = Builder.CreateIntrinsic(
+ ShuffleDstTy, IID, {Shuf, cast<Constant>(II0->getArgOperand(1))});
+ Worklist.pushValue(Shuf);
+ break;
+ }
+ default:
+ llvm_unreachable("Unexpected intrinsic");
+ }
+
+ // Intersect flags from the old intrinsics.
+ if (auto *NewInst = dyn_cast<Instruction>(NewIntrinsic)) {
+ NewInst->copyIRFlags(II0);
+ NewInst->andIRFlags(II1);
+ }
+
+ replaceValue(I, *NewIntrinsic);
+ return true;
+}
+
using InstLane = std::pair<Use *, int>;
static InstLane lookThroughShuffles(Use *U, int Lane) {
@@ -2554,6 +2647,7 @@ bool VectorCombine::run() {
MadeChange |= foldShuffleOfBinops(I);
MadeChange |= foldShuffleOfCastops(I);
MadeChange |= foldShuffleOfShuffles(I);
+ MadeChange |= foldShuffleOfIntrinsics(I);
MadeChange |= foldSelectShuffle(I);
MadeChange |= foldShuffleToIdentity(I);
break;
diff --git a/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
index ba45f24929c71e..32a11a7d813b28 100644
--- a/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
+++ b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
@@ -4,10 +4,9 @@
define <8 x i32> @test1(<4 x i32> %0, <4 x i32> %1) {
; CHECK-LABEL: @test1(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP0:%.*]], i1 false)
-; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP1:%.*]], i1 false)
-; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: ret <8 x i32> [[TMP4]]
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP0:%.*]], <4 x i32> [[TMP1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i32> @llvm.abs.v8i32(<8 x i32> [[TMP2]], i1 false)
+; CHECK-NEXT: ret <8 x i32> [[TMP3]]
;
entry:
%2 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %0, i1 false)
>From da5fb67949f4dbfda52732955b0cc24fb7f344b7 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Fri, 30 Aug 2024 00:38:44 -0700
Subject: [PATCH 3/4] [VectorCombine] Pre-commit test.
---
.../VectorCombine/foldShuffleOfIntrinsics.ll | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
index 32a11a7d813b28..747caa6689ae78 100644
--- a/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
+++ b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
@@ -30,4 +30,53 @@ entry:
ret <8 x i32> %4
}
+define <8 x i32> @test3(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP0:%.*]], <4 x i32> [[TMP1:%.*]])
+; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP2:%.*]], <4 x i32> [[TMP3:%.*]])
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: ret <8 x i32> [[TMP6]]
+;
+entry:
+ %4 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %0, <4 x i32> %1)
+ %5 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %2, <4 x i32> %3)
+ %6 = shufflevector <4 x i32> %4, <4 x i32> %5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i32> %6
+}
+
+define <8 x i1> @test4(<4 x float> %0, <4 x float> %1) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP0:%.*]], i32 0)
+; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP1:%.*]], i32 0)
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: ret <8 x i1> [[TMP4]]
+;
+entry:
+ %2 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %0, i32 0)
+ %3 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %1, i32 0)
+ %4 = shufflevector <4 x i1> %2, <4 x i1> %3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x i1> %4
+}
+
+define <8 x float> @test5(<4 x float> %0, i32 %1, <4 x float> %2, <4 x i32> %3) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> [[TMP0:%.*]], i32 [[TMP1:%.*]])
+; CHECK-NEXT: [[TMP5:%.*]] = call <4 x float> @llvm.powi.v4f32.v4i32(<4 x float> [[TMP2:%.*]], <4 x i32> [[TMP3:%.*]])
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: ret <8 x float> [[TMP6]]
+;
+entry:
+ %4 = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %0, i32 %1)
+ %5 = call <4 x float> @llvm.powi.v4f32.v4i32(<4 x float> %2, <4 x i32> %3)
+ %6 = shufflevector <4 x float> %4, <4 x float> %5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ ret <8 x float> %6
+}
+
declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
+declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i1> @llvm.is.fpclass.v4f32(<4 x float>, i32)
+declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32)
+declare <4 x float> @llvm.powi.v4f32.v4i32(<4 x float>, <4 x i32>)
>From 3c51d3d317de39dbbe676cbd380ca94e877ae003 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Fri, 30 Aug 2024 00:56:44 -0700
Subject: [PATCH 4/4] [VectorCombine] Apply comment.
---
.../Transforms/Vectorize/VectorCombine.cpp | 64 +++++++++----------
.../VectorCombine/foldShuffleOfIntrinsics.ll | 13 ++--
2 files changed, 36 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 9ad7276ffb9707..4a5077cecbfeba 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -1697,16 +1697,13 @@ bool VectorCombine::foldShuffleOfIntrinsics(Instruction &I) {
if (!ShuffleDstTy || !II0Ty)
return false;
- switch (IID) {
- case Intrinsic::abs: {
- if (cast<Constant>(II0->getArgOperand(1))->isOneValue() !=
- cast<Constant>(II1->getArgOperand(1))->isOneValue())
- return false;
- break;
- }
- default:
+ if (!isTriviallyVectorizable(IID))
return false;
- }
+
+ for (unsigned I = 0; I != II0->arg_size(); ++I)
+ if (isVectorIntrinsicWithScalarOpAtArg(IID, I) &&
+ II0->getArgOperand(I) != II1->getArgOperand(I))
+ return false;
SmallVector<Value *> Args0;
SmallVector<Value *> Args1;
@@ -1722,19 +1719,20 @@ bool VectorCombine::foldShuffleOfIntrinsics(Instruction &I) {
TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, II0Ty, OldMask,
TTI::TCK_RecipThroughput, 0, nullptr, {II0, II1}, &I);
- InstructionCost NewCost;
- switch (IID) {
- case Intrinsic::abs: {
- IntrinsicCostAttributes NewAttr(IID, ShuffleDstTy,
- {ShuffleDstTy, Builder.getInt1Ty()});
- NewCost = TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, II0Ty,
- OldMask, TTI::TCK_RecipThroughput) +
- TTI.getIntrinsicInstrCost(NewAttr, TTI::TCK_RecipThroughput);
- break;
- }
- default:
- llvm_unreachable("Unexpected intrinsic");
- }
+ SmallVector<Type *> NewArgsTy;
+ InstructionCost NewCost = 0;
+ for (unsigned I = 0; I != II0->arg_size(); ++I)
+ if (isVectorIntrinsicWithScalarOpAtArg(IID, I)) {
+ NewArgsTy.push_back(Args0[I]->getType());
+ } else {
+ auto *VecTy = cast<FixedVectorType>(Args0[I]->getType());
+ NewArgsTy.push_back(FixedVectorType::get(VecTy->getElementType(),
+ VecTy->getNumElements() * 2));
+ NewCost += TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc,
+ VecTy, OldMask, TTI::TCK_RecipThroughput);
+ }
+ IntrinsicCostAttributes NewAttr(IID, ShuffleDstTy, NewArgsTy);
+ NewCost += TTI.getIntrinsicInstrCost(NewAttr, TTI::TCK_RecipThroughput);
LLVM_DEBUG(dbgs() << "Found a shuffle feeding two intrinsics: " << I
<< "\n OldCost: " << OldCost << " vs NewCost: " << NewCost
@@ -1743,18 +1741,16 @@ bool VectorCombine::foldShuffleOfIntrinsics(Instruction &I) {
if (NewCost > OldCost)
return false;
- Value *NewIntrinsic;
- switch (IID) {
- case Intrinsic::abs: {
- Value *Shuf = Builder.CreateShuffleVector(Args0[0], Args1[0], OldMask);
- NewIntrinsic = Builder.CreateIntrinsic(
- ShuffleDstTy, IID, {Shuf, cast<Constant>(II0->getArgOperand(1))});
- Worklist.pushValue(Shuf);
- break;
- }
- default:
- llvm_unreachable("Unexpected intrinsic");
- }
+ SmallVector<Value *> NewArgs;
+ for (unsigned I = 0; I != II0->arg_size(); ++I)
+ if (isVectorIntrinsicWithScalarOpAtArg(IID, I)) {
+ NewArgs.push_back(II0->getArgOperand(I));
+ } else {
+ Value *Shuf = Builder.CreateShuffleVector(Args0[I], Args1[I], OldMask);
+ NewArgs.push_back(Shuf);
+ Worklist.pushValue(Shuf);
+ }
+ Value *NewIntrinsic = Builder.CreateIntrinsic(ShuffleDstTy, IID, NewArgs);
// Intersect flags from the old intrinsics.
if (auto *NewInst = dyn_cast<Instruction>(NewIntrinsic)) {
diff --git a/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
index 747caa6689ae78..b9c8e795ad5e73 100644
--- a/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
+++ b/llvm/test/Transforms/VectorCombine/foldShuffleOfIntrinsics.ll
@@ -33,9 +33,9 @@ entry:
define <8 x i32> @test3(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3) {
; CHECK-LABEL: @test3(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP0:%.*]], <4 x i32> [[TMP1:%.*]])
-; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP2:%.*]], <4 x i32> [[TMP3:%.*]])
-; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP4]], <4 x i32> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP0:%.*]], <4 x i32> [[TMP2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP1:%.*]], <4 x i32> [[TMP3:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP6:%.*]] = call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[TMP4]], <8 x i32> [[TMP5]])
; CHECK-NEXT: ret <8 x i32> [[TMP6]]
;
entry:
@@ -48,10 +48,9 @@ entry:
define <8 x i1> @test4(<4 x float> %0, <4 x float> %1) {
; CHECK-LABEL: @test4(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP0:%.*]], i32 0)
-; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> [[TMP1:%.*]], i32 0)
-; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i1> [[TMP2]], <4 x i1> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT: ret <8 x i1> [[TMP4]]
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> [[TMP2]], i32 0)
+; CHECK-NEXT: ret <8 x i1> [[TMP3]]
;
entry:
%2 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %0, i32 0)
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