[llvm] [Mips] Add test file for 'xor' and 'and' instructions (PR #106679)

[via llvm-commits]

https://github.com/anbbna created https://github.com/llvm/llvm-project/pull/106679

Part of #99783 

This test is meant to reflect the oncoming change as this test shows the unoptimized result with unnecessary SLLs.

>From 0adf3499784a53d80bc87512b88110a98a276cf7 Mon Sep 17 00:00:00 2001
From: anbb <beibei.an at oss.cipunited.com>
Date: Thu, 29 Aug 2024 06:50:36 -0400
Subject: [PATCH] [Mips]Add test file for 'xor' and 'and' instructions

For llvm#99783
---
 llvm/test/CodeGen/Mips/xor-and.ll | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 llvm/test/CodeGen/Mips/xor-and.ll

diff --git a/llvm/test/CodeGen/Mips/xor-and.ll b/llvm/test/CodeGen/Mips/xor-and.ll
new file mode 100644
index 00000000000000..6d78ce7c22950a
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/xor-and.ll
@@ -0,0 +1,16 @@
+; RUN: llc -O3 -mcpu=mips64r6 -mtriple=mips64el-unknown-linux-gnuabi64 < %s -o - | FileCheck %s
+
+define noundef signext i32 @xor_and(i32 noundef signext %a, i32 noundef signext %b) local_unnamed_addr {
+; CHECK-LABEL: xor_and:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    and $1, $5, $4
+; CHECK-NEXT:    sll $1, $1, 0
+; CHECK-NEXT:    not $1, $1
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    sll $2, $1, 0
+
+entry:
+  %0 = and i32 %b, %a
+  %or1 = xor i32 %0, -1
+  ret i32 %or1
+}