[llvm] BPF: Generate locked insn for __sync_fetch_and_add() with cpu v1/v2 (PR #106494)

[via llvm-commits]

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@@ -806,6 +806,7 @@ class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
 let Constraints = "$dst = $val" in {
   let Predicates = [BPFNoALU32] in {
     def XADDW : XADD<BPF_W, "u32", atomic_load_add_i32>;
+    def XADDD : XADD<BPF_DW, "u64", atomic_load_add_i64>;
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yonghong-song wrote:

@eddyz87 I checked your code. It won't work because with BPFNoALU32 does not allow sub-registers. In current implementation, 64bit atomic_nofetch insns are available at cpu v1, but 32bit atomic nofetch (except xadd) are not available at cpu v1. so 32bit xadd needs specialization anyway. so your approach will work for 64bit xaddd, but not for xadd. So I suggest to use the current implementation. Let me know what you think.

https://github.com/llvm/llvm-project/pull/106494