[llvm] [RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (PR #106653)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 29 19:12:21 PDT 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/106653
>From 153bc353f059ddf94c4e1e78f6eb9ed90770f257 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 29 Aug 2024 19:08:31 -0700
Subject: [PATCH 1/2] [RISCV] Add constant folding combine for FMV_X_ANYEXTW/H.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +++++++
llvm/test/CodeGen/RISCV/calling-conv-half.ll | 9 +++------
llvm/test/CodeGen/RISCV/float-imm.ll | 4 ++--
llvm/test/CodeGen/RISCV/half-imm.ll | 14 ++++----------
4 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 09928dcc1f489a..33bc4b063bbb48 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16440,6 +16440,13 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
SDLoc DL(N);
SDValue Op0 = N->getOperand(0);
MVT VT = N->getSimpleValueType(0);
+
+ // Constant fold.
+ if (auto *CFP = dyn_cast<ConstantFPSDNode>(Op0)) {
+ APInt Val = CFP->getValueAPF().bitcastToAPInt().sext(VT.getSizeInBits());
+ return DAG.getConstant(Val, DL, VT);
+ }
+
// If the input to FMV_X_ANYEXTW_RV64 is just FMV_W_X_RV64 then the
// conversion is unnecessary and can be replaced with the FMV_W_X_RV64
// operand. Similar for FMV_X_ANYEXTH and FMV_H_X.
diff --git a/llvm/test/CodeGen/RISCV/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/calling-conv-half.ll
index c88b2bf596ca23..cccb69d2e6986a 100644
--- a/llvm/test/CodeGen/RISCV/calling-conv-half.ll
+++ b/llvm/test/CodeGen/RISCV/calling-conv-half.ll
@@ -161,10 +161,8 @@ define i32 @caller_half_in_regs() nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64IF-NEXT: lui a0, 1048564
-; RV64IF-NEXT: fmv.w.x fa5, a0
-; RV64IF-NEXT: fmv.x.w a1, fa5
; RV64IF-NEXT: li a0, 1
+; RV64IF-NEXT: lui a1, 1048564
; RV64IF-NEXT: call callee_half_in_regs
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
@@ -511,9 +509,8 @@ define half @callee_half_ret() nounwind {
;
; RV64IF-LABEL: callee_half_ret:
; RV64IF: # %bb.0:
-; RV64IF-NEXT: lui a0, %hi(.LCPI4_0)
-; RV64IF-NEXT: flw fa5, %lo(.LCPI4_0)(a0)
-; RV64IF-NEXT: fmv.x.w a0, fa5
+; RV64IF-NEXT: lui a0, 1048564
+; RV64IF-NEXT: addiw a0, a0, -1024
; RV64IF-NEXT: ret
;
; RV32-ILP32F-LABEL: callee_half_ret:
diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll
index c38416d994ba57..69a506cd850f2c 100644
--- a/llvm/test/CodeGen/RISCV/float-imm.ll
+++ b/llvm/test/CodeGen/RISCV/float-imm.ll
@@ -24,8 +24,8 @@ define float @float_imm() nounwind {
;
; RV64ZFINX-LABEL: float_imm:
; RV64ZFINX: # %bb.0:
-; RV64ZFINX-NEXT: lui a0, %hi(.LCPI0_0)
-; RV64ZFINX-NEXT: lw a0, %lo(.LCPI0_0)(a0)
+; RV64ZFINX-NEXT: lui a0, 263313
+; RV64ZFINX-NEXT: addiw a0, a0, -37
; RV64ZFINX-NEXT: ret
ret float 3.14159274101257324218750
}
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
index 9c11010540e15d..f2292b656a304f 100644
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -30,14 +30,14 @@ define half @half_imm() nounwind {
;
; RV32IZHINX-LABEL: half_imm:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: lui a0, %hi(.LCPI0_0)
-; RV32IZHINX-NEXT: lh a0, %lo(.LCPI0_0)(a0)
+; RV32IZHINX-NEXT: lui a0, 4
+; RV32IZHINX-NEXT: addi a0, a0, 512
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: half_imm:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: lui a0, %hi(.LCPI0_0)
-; RV64IZHINX-NEXT: lh a0, %lo(.LCPI0_0)(a0)
+; RV64IZHINX-NEXT: lui a0, 4
+; RV64IZHINX-NEXT: addiw a0, a0, 512
; RV64IZHINX-NEXT: ret
;
; CHECKIZFHMIN-LABEL: half_imm:
@@ -45,12 +45,6 @@ define half @half_imm() nounwind {
; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI0_0)
; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECKIZFHMIN-NEXT: ret
-;
-; CHECKIZHINXMIN-LABEL: half_imm:
-; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: lui a0, %hi(.LCPI0_0)
-; CHECKIZHINXMIN-NEXT: lh a0, %lo(.LCPI0_0)(a0)
-; CHECKIZHINXMIN-NEXT: ret
ret half 3.0
}
>From 5c0c640f62dfed1b217d78bc05795202db3171e1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 29 Aug 2024 19:12:08 -0700
Subject: [PATCH 2/2] fixup! Fix check-prefix conflict
---
llvm/test/CodeGen/RISCV/half-imm.ll | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll
index f2292b656a304f..4c39885176f01a 100644
--- a/llvm/test/CodeGen/RISCV/half-imm.ll
+++ b/llvm/test/CodeGen/RISCV/half-imm.ll
@@ -15,10 +15,10 @@
; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: -target-abi ilp32 < %s \
-; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN %s
+; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
; RUN: -target-abi lp64 < %s \
-; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN %s
+; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
define half @half_imm() nounwind {
@@ -45,6 +45,18 @@ define half @half_imm() nounwind {
; CHECKIZFHMIN-NEXT: lui a0, %hi(.LCPI0_0)
; CHECKIZFHMIN-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECKIZFHMIN-NEXT: ret
+;
+; RV32IZHINXMIN-LABEL: half_imm:
+; RV32IZHINXMIN: # %bb.0:
+; RV32IZHINXMIN-NEXT: lui a0, 4
+; RV32IZHINXMIN-NEXT: addi a0, a0, 512
+; RV32IZHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: half_imm:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: lui a0, 4
+; RV64IZHINXMIN-NEXT: addiw a0, a0, 512
+; RV64IZHINXMIN-NEXT: ret
ret half 3.0
}
More information about the llvm-commits
mailing list