[llvm] [LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (PR #106652)

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git-clang-format --diff cc943a67d114e28c28f561c3b1a48ff2003264ce 83975c9adf3181fed7e4a8050d83e6e17f836360 --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index b551462831..1a87497900 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -1698,8 +1698,7 @@ SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {
   EVT IntVT = VT.changeVectorElementTypeToInteger();
 
   // FIXME: We shouldn't restrict this to scalable vectors.
-  if (TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) &&
-      VT.isScalableVector()) {
+  if (TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) && VT.isScalableVector()) {
     SDLoc DL(Node);
     SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
     SDValue ClearSignMask = DAG.getConstant(
@@ -1717,8 +1716,7 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
   // FIXME: We shouldn't restrict this to scalable vectors.
   if (VT == Node->getOperand(1).getValueType() &&
       TLI.isOperationLegalOrCustom(ISD::AND, IntVT) &&
-      TLI.isOperationLegalOrCustom(ISD::OR, IntVT) &&
-      VT.isScalableVector()) {
+      TLI.isOperationLegalOrCustom(ISD::OR, IntVT) && VT.isScalableVector()) {
     SDLoc DL(Node);
     SDValue Mag = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
     SDValue Sign = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(1));
@@ -1734,7 +1732,8 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {
     SDNodeFlags Flags;
     Flags.setDisjoint(true);
 
-    SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit, Flags);
+    SDValue CopiedSign =
+        DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit, Flags);
 
     return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);
   }
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cddd65f58b..b402089e48 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -882,13 +882,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
     // TODO: support more ops.
     static const unsigned ZvfhminPromoteOps[] = {
-        ISD::FMINNUM,     ISD::FMAXNUM,      ISD::FADD,        ISD::FSUB,
-        ISD::FMUL,        ISD::FMA,          ISD::FDIV,        ISD::FSQRT,
-        ISD::FCEIL,
-        ISD::FFLOOR,      ISD::FROUND,       ISD::FROUNDEVEN,  ISD::FRINT,
-        ISD::FNEARBYINT,  ISD::IS_FPCLASS,   ISD::SETCC,       ISD::FMAXIMUM,
-        ISD::FMINIMUM,    ISD::STRICT_FADD,  ISD::STRICT_FSUB, ISD::STRICT_FMUL,
-        ISD::STRICT_FDIV, ISD::STRICT_FSQRT, ISD::STRICT_FMA};
+        ISD::FMINNUM,     ISD::FMAXNUM,     ISD::FADD,         ISD::FSUB,
+        ISD::FMUL,        ISD::FMA,         ISD::FDIV,         ISD::FSQRT,
+        ISD::FCEIL,       ISD::FFLOOR,      ISD::FROUND,       ISD::FROUNDEVEN,
+        ISD::FRINT,       ISD::FNEARBYINT,  ISD::IS_FPCLASS,   ISD::SETCC,
+        ISD::FMAXIMUM,    ISD::FMINIMUM,    ISD::STRICT_FADD,  ISD::STRICT_FSUB,
+        ISD::STRICT_FMUL, ISD::STRICT_FDIV, ISD::STRICT_FSQRT, ISD::STRICT_FMA};
 
     // TODO: support more vp ops.
     static const unsigned ZvfhminPromoteVPOps[] = {

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https://github.com/llvm/llvm-project/pull/106652