[llvm] 4ca817d - [GlobalISel] Add bail outs for scalable vectors to some combines. (#106496)

[via llvm-commits]

Author: Craig Topper
Date: 2024-08-29T14:02:53-07:00
New Revision: 4ca817d0511b2c36b2f5d242e0c8f90a7a9c4f14

URL: https://github.com/llvm/llvm-project/commit/4ca817d0511b2c36b2f5d242e0c8f90a7a9c4f14
DIFF: https://github.com/llvm/llvm-project/commit/4ca817d0511b2c36b2f5d242e0c8f90a7a9c4f14.diff

LOG: [GlobalISel] Add bail outs for scalable vectors to some combines. (#106496)

These combines call getNumElements() which isn't valid for scalable
vectors.

Added: 
    llvm/test/CodeGen/RISCV/GlobalISel/scalablevec-combiner-crash.ll

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 1517ae707c8cff..df9c12bc9c97bd 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2678,6 +2678,9 @@ bool CombinerHelper::matchInsertExtractVecEltOutOfBounds(MachineInstr &MI) {
           MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT) &&
          "Expected an insert/extract element op");
   LLT VecTy = MRI.getType(MI.getOperand(1).getReg());
+  if (VecTy.isScalableVector())
+    return false;
+
   unsigned IdxIdx =
       MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
   auto Idx = getIConstantVRegVal(MI.getOperand(IdxIdx).getReg(), MRI);
@@ -2961,6 +2964,10 @@ bool CombinerHelper::matchCombineInsertVecElts(
   Register DstReg = MI.getOperand(0).getReg();
   LLT DstTy = MRI.getType(DstReg);
   assert(DstTy.isVector() && "Invalid G_INSERT_VECTOR_ELT?");
+
+  if (DstTy.isScalableVector())
+    return false;
+
   unsigned NumElts = DstTy.getNumElements();
   // If this MI is part of a sequence of insert_vec_elts, then
   // don't do the combine in the middle of the sequence.
@@ -4046,6 +4053,8 @@ bool CombinerHelper::matchExtractVecEltBuildVec(MachineInstr &MI,
   // and find the source register that the index maps to.
   Register SrcVec = MI.getOperand(1).getReg();
   LLT SrcTy = MRI.getType(SrcVec);
+  if (SrcTy.isScalableVector())
+    return false;
 
   auto Cst = getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI);
   if (!Cst || Cst->Value.getZExtValue() >= SrcTy.getNumElements())

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/scalablevec-combiner-crash.ll b/llvm/test/CodeGen/RISCV/GlobalISel/scalablevec-combiner-crash.ll
new file mode 100644
index 00000000000000..8ce4b334a5134c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/scalablevec-combiner-crash.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -global-isel -stop-after=riscv-prelegalizer-combiner | FileCheck %s
+
+; Make sure we don't crash in the prelegalizer combiner for scalable vector
+; insert and extracts.
+
+define <vscale x 1 x i1> @insertelement_nxv1i1_0(<vscale x 1 x i1> %x) {
+  ; CHECK-LABEL: name: insertelement_nxv1i1_0
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+  ; CHECK-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[C]](s1), [[C1]](s64)
+  ; CHECK-NEXT:   $v0 = COPY [[IVEC]](<vscale x 1 x s1>)
+  ; CHECK-NEXT:   PseudoRET implicit $v0
+  %a = insertelement <vscale x 1 x i1> %x, i1 0, i32 0
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @shufflevector_nxv1i1_0(<vscale x 1 x i1> %x) {
+  ; CHECK-LABEL: name: shufflevector_nxv1i1_0
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $v0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0
+  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+  ; CHECK-NEXT:   [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s1>), [[C]](s64)
+  ; CHECK-NEXT:   [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1)
+  ; CHECK-NEXT:   $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)
+  ; CHECK-NEXT:   PseudoRET implicit $v0
+  %a = shufflevector <vscale x 1 x i1> %x, <vscale x 1 x i1> poison, <vscale x 1 x i32> poison
+  ret <vscale x 1 x i1> %a
+}