[llvm] [AArch64][AsmParser] Directives should clear transitively implied features (PR #106625)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 29 13:52:11 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Alexandros Lamprineas (labrinea)
<details>
<summary>Changes</summary>
The commit ff3f3a54e2d1 made it possible to enable transitively implied features when parsing assembler directives. For example enabling sve2 also enables sve.
This patch allows disabling features which depend on each other. For example disabling sve also disables sve2.
---
Full diff: https://github.com/llvm/llvm-project/pull/106625.diff
5 Files Affected:
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+19-18)
- (added) llvm/test/MC/AArch64/SVE/directive-arch-negative.s (+8)
- (modified) llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s (+6-1)
- (modified) llvm/test/MC/AArch64/SVE/directive-cpu-negative.s (+6-1)
- (modified) llvm/test/MC/AArch64/directive-arch_extension-negative.s (+12)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 37add682b150e7..12241b6b3f4eb7 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6991,11 +6991,12 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) {
if (Extension.Features.none())
report_fatal_error("unsupported architectural extension: " + Name);
- FeatureBitset ToggleFeatures =
- EnableFeature
- ? STI.SetFeatureBitsTransitively(~Features & Extension.Features)
- : STI.ToggleFeature(Features & Extension.Features);
- setAvailableFeatures(ComputeAvailableFeatures(ToggleFeatures));
+ if (EnableFeature)
+ STI.SetFeatureBitsTransitively(Extension.Features);
+ else
+ STI.ClearFeatureBitsTransitively(Extension.Features);
+ FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
+ setAvailableFeatures(Features);
break;
}
}
@@ -7018,8 +7019,6 @@ bool AArch64AsmParser::parseDirectiveArchExtension(SMLoc L) {
Name = Name.substr(2);
}
- MCSubtargetInfo &STI = copySTI();
- FeatureBitset Features = STI.getFeatureBits();
for (const auto &Extension : ExtensionMap) {
if (Extension.Name != Name)
continue;
@@ -7027,11 +7026,13 @@ bool AArch64AsmParser::parseDirectiveArchExtension(SMLoc L) {
if (Extension.Features.none())
return Error(ExtLoc, "unsupported architectural extension: " + Name);
- FeatureBitset ToggleFeatures =
- EnableFeature
- ? STI.SetFeatureBitsTransitively(~Features & Extension.Features)
- : STI.ToggleFeature(Features & Extension.Features);
- setAvailableFeatures(ComputeAvailableFeatures(ToggleFeatures));
+ MCSubtargetInfo &STI = copySTI();
+ if (EnableFeature)
+ STI.SetFeatureBitsTransitively(Extension.Features);
+ else
+ STI.ClearFeatureBitsTransitively(Extension.Features);
+ FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
+ setAvailableFeatures(Features);
return false;
}
@@ -7083,12 +7084,12 @@ bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) {
if (Extension.Features.none())
report_fatal_error("unsupported architectural extension: " + Name);
- FeatureBitset Features = STI.getFeatureBits();
- FeatureBitset ToggleFeatures =
- EnableFeature
- ? STI.SetFeatureBitsTransitively(~Features & Extension.Features)
- : STI.ToggleFeature(Features & Extension.Features);
- setAvailableFeatures(ComputeAvailableFeatures(ToggleFeatures));
+ if (EnableFeature)
+ STI.SetFeatureBitsTransitively(Extension.Features);
+ else
+ STI.ClearFeatureBitsTransitively(Extension.Features);
+ FeatureBitset Features = ComputeAvailableFeatures(STI.getFeatureBits());
+ setAvailableFeatures(Features);
FoundExtension = true;
break;
diff --git a/llvm/test/MC/AArch64/SVE/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE/directive-arch-negative.s
new file mode 100644
index 00000000000000..e3029c16ffc8a6
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/directive-arch-negative.s
@@ -0,0 +1,8 @@
+// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+// Check that setting +nosve implies +nosve2
+.arch armv9-a+nosve
+
+adclb z0.s, z1.s, z31.s
+// CHECK: error: instruction requires: sve2
+// CHECK-NEXT: adclb z0.s, z1.s, z31.s
diff --git a/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s
index 661f13974d0bc8..31118f7490d00d 100644
--- a/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE/directive-arch_extension-negative.s
@@ -1,7 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.arch_extension nosve
+.arch_extension sve2+nosve
ptrue p0.b, pow2
// CHECK: error: instruction requires: sve or sme
// CHECK-NEXT: ptrue p0.b, pow2
+
+// Check that setting +nosve implies +nosve2
+adclb z0.s, z1.s, z31.s
+// CHECK: error: instruction requires: sve2
+// CHECK-NEXT: adclb z0.s, z1.s, z31.s
diff --git a/llvm/test/MC/AArch64/SVE/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE/directive-cpu-negative.s
index 82acc1b0b0be9b..6ba537ca70609e 100644
--- a/llvm/test/MC/AArch64/SVE/directive-cpu-negative.s
+++ b/llvm/test/MC/AArch64/SVE/directive-cpu-negative.s
@@ -1,6 +1,11 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.cpu generic+sve+nosve
+.cpu generic+sve2+nosve
ptrue p0.b, pow2
// CHECK: error: instruction requires: sve or sme
// CHECK-NEXT: ptrue p0.b, pow2
+
+// Check that setting +nosve implies +nosve2
+adclb z0.s, z1.s, z31.s
+// CHECK: error: instruction requires: sve2
+// CHECK-NEXT: adclb z0.s, z1.s, z31.s
diff --git a/llvm/test/MC/AArch64/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
index 1c1cfc9d33e3ed..d8f7fa1d7b791b 100644
--- a/llvm/test/MC/AArch64/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/directive-arch_extension-negative.s
@@ -49,6 +49,8 @@ fminnm d0, d0, d1
// CHECK: [[@LINE-1]]:1: error: instruction requires: fp
// CHECK-NEXT: fminnm d0, d0, d1
+// nofp implied nosimd, so reinstate it
+.arch_extension simd
addp v0.4s, v0.4s, v0.4s
// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: neon
.arch_extension nosimd
@@ -70,6 +72,8 @@ casa w5, w7, [x20]
// CHECK: [[@LINE-1]]:1: error: instruction requires: lse
// CHECK-NEXT: casa w5, w7, [x20]
+// nolse implied nolse128, so reinstate it
+.arch_extension lse128
swpp x0, x2, [x3]
// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: lse128
.arch_extension nolse128
@@ -84,6 +88,8 @@ cfp rctx, x0
// CHECK: [[@LINE-1]]:5: error: CFPRCTX requires: predres
// CHECK-NEXT: cfp rctx, x0
+// nopredres implied nopredres2, so reinstate it
+.arch_extension predres2
cosp rctx, x0
// CHECK-NOT: [[@LINE-1]]:6: error: COSP requires: predres2
.arch_extension nopredres2
@@ -133,6 +139,8 @@ ldapr x0, [x1]
// CHECK: [[@LINE-1]]:1: error: instruction requires: rcpc
// CHECK-NEXT: ldapr x0, [x1]
+// norcpc implied norcpc3, so reinstate it
+.arch_extension rcpc3
stilp w24, w0, [x16, #-8]!
// CHECK-NOT: [[@LINE-1]]:1: error: instruction requires: rcpc3
.arch_extension norcpc3
@@ -169,6 +177,8 @@ cpyfp [x0]!, [x1]!, x2!
// CHECK: [[@LINE-1]]:1: error: instruction requires: mops
// CHECK-NEXT: cpyfp [x0]!, [x1]!, x2!
+// nolse128 implied nod128, so reinstate it
+.arch_extension d128
// This needs to come before `.arch_extension nothe` as it uses an instruction
// that requires both the and d128
sysp #0, c2, c0, #0, x0, x1
@@ -204,6 +214,8 @@ umax x0, x1, x2
// CHECK: [[@LINE-1]]:1: error: instruction requires: cssc
// CHECK-NEXT: umax x0, x1, x2
+// noras implied norasv2, so reinstate it
+.arch_extension rasv2
mrs x0, ERXGSR_EL1
// CHECK-NOT: [[@LINE-1]]:9: error: expected readable system register
.arch_extension norasv2
``````````
</details>
https://github.com/llvm/llvm-project/pull/106625
More information about the llvm-commits
mailing list