[llvm] [ExtendLifetimes] Implement llvm.fake.use to extend variable lifetimes (PR #86149)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `clang-aarch64-sve-vla` running on `linaro-g3-03` while building `llvm` at step 7 "ninja check 1".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/17/builds/2296

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 7 (ninja check 1) failure: stage 1 checked (failure)
******************** TEST 'LLVM :: CodeGen/X86/fake-use-scheduler.mir' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/stage1/bin/llc -run-pass machine-scheduler -debug-only=machine-scheduler 2>&1 -o - /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir | /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/stage1/bin/FileCheck /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir
+ /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/stage1/bin/llc -run-pass machine-scheduler -debug-only=machine-scheduler -o - /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir
+ /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/stage1/bin/FileCheck /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir
/home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir:10:10: error: CHECK: expected string not found in input
# CHECK: ********** MI Scheduling **********
         ^
<stdin>:1:1: note: scanning from here
error: /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir:69:21: use of undefined register class or register bank 'gr64'
^
<stdin>:1:79: note: possible intended match here
error: /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir:69:21: use of undefined register class or register bank 'gr64'
                                                                              ^

Input file: <stdin>
Check file: /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir

-dump-input=help explains the following input dump.

Input was:
<<<<<<
            1: error: /home/tcwg-buildbot/worker/clang-aarch64-sve-vla/llvm/llvm/test/CodeGen/X86/fake-use-scheduler.mir:69:21: use of undefined register class or register bank 'gr64' 
check:10'0     X~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ error: no match found
check:10'1                                                                                   ?                                                                                           possible intended match
            2:  - { id: 0, class: gr64, preferred-register: '' } 
check:10'0     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            3:  ^ 
check:10'0     ~~~
            4:  
check:10'0     ~
>>>>>>

--

********************


```

</details>

https://github.com/llvm/llvm-project/pull/86149