[llvm] [RISCV][SiFive7] Change `Latency` of VCIX to the default (PR #106497)

[Craig Topper via llvm-commits]

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@@ -966,14 +966,14 @@ def : InstRW<[WriteIALU], (instrs COPY)>;
 // VCIX
 //
 // In principle we don't know the latency of any VCIX instructions. But instead
-// of taking the default of 1, which can lead to issues [1], we assume that they
-// have a fairly high latency.
+// of taking the default of 1, which can lead to issues [1], we use the default
+// latency provided by `SiFive7GetCyclesDefault`.
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topperc wrote:

Isn't the behavior of SiFive7GetCyclesDefault LMul*2 not 1.?

https://github.com/llvm/llvm-project/pull/106497