[llvm] 36b7c30 - [X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVEX.pp = 01 (#103816)

[via llvm-commits]

Author: Freddy Ye
Date: 2024-08-29T18:22:26+08:00
New Revision: 36b7c30b292f853c09b80f8bc2c5f233f68c9e7b

URL: https://github.com/llvm/llvm-project/commit/36b7c30b292f853c09b80f8bc2c5f233f68c9e7b
DIFF: https://github.com/llvm/llvm-project/commit/36b7c30b292f853c09b80f8bc2c5f233f68c9e7b.diff

LOG: [X86, MC] Recognize OSIZE=64b when EVEX.W = 1, EVEX.pp = 01 (#103816)

In the legacy space, if both the 66 prefix and REX.W=1 are present, the
REX.W=1 takes precedence and makes OSIZE=64b. EVEX map 4 inherits this
convention, with EVEX.pp=01 and EVEX.W playing the roles of the 66
prefix and REX.W. So if EVEX.pp=00, the OSIZE can only be 64b or 32b,
depending on whether EVEX.W=1 or not. But if EVEX.pp=01, then OSIZE is
either 64b or 16b depending on whether EVEX.W=1 or not.

Added: 
    llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt

Modified: 
    llvm/utils/TableGen/X86DisassemblerTables.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
new file mode 100644
index 00000000000000..e8ab9b5c853f0c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
@@ -0,0 +1,116 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+## This test is to check OSIZE=64b when EVEX.W=1 and EVEX.pp = 01.
+
+## adc
+# ATT:   {evex}  adcq    $123, %r9
+# INTEL: {evex}  adc     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xd1,0x7b
+
+# ATT:   adcq    $123, %r9, %r10
+# INTEL: adc     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xd1,0x7b
+
+## add
+# ATT:   {evex}  addq    $123, %r9
+# INTEL: {evex}  add     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xc1,0x7b
+
+# ATT:   addq    $123, %r9, %r10
+# INTEL: add     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xc1,0x7b
+
+# ATT:   {nf} addq $123, %r9
+# INTEL: {nf} add  r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xc1,0x7b
+
+# ATT:   {nf} addq $123, %r9, %r10
+# INTEL: {nf} add  r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xc1,0x7b
+
+## sbb
+# ATT:   {evex}  sbbq    $123, %r9
+# INTEL: {evex}  sbb     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xd9,0x7b
+
+# ATT:   sbbq    $123, %r9, %r10
+# INTEL: sbb     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xd9,0x7b
+
+## sub
+# ATT:   {evex}  subq    $123, %r9
+# INTEL: {evex}  sub     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xe9,0x7b
+
+# ATT:   subq    $123, %r9, %r10
+# INTEL: sub     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xe9,0x7b
+
+# ATT:   {nf} subq $123, %r9
+# INTEL: {nf} sub  r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xe9,0x7b
+
+# ATT:   {nf} subq $123, %r9, %r10
+# INTEL: {nf} sub  r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xe9,0x7b
+
+## imul
+# ATT:   {evex}  imulq    $123, %r9, %r10
+# INTEL: {evex}  imul     r10, r9, 123
+0x62,0x54,0xfd,0x08,0x6b,0xd1,0x7b
+
+# ATT:   {nf} imulq    $123, %r9, %r10
+# INTEL: {nf} imul     r10, r9, 123
+0x62,0x54,0xfd,0x0c,0x6b,0xd1,0x7b
+
+## and
+# ATT:   {evex}  andq    $123, %r9
+# INTEL: {evex}  and     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xe1,0x7b
+
+# ATT:   andq    $123, %r9, %r10
+# INTEL: and     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xe1,0x7b
+
+# ATT:   {nf} andq $123, %r9
+# INTEL: {nf} and  r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xe1,0x7b
+
+# ATT:   {nf} andq $123, %r9, %r10
+# INTEL: {nf} and  r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xe1,0x7b
+
+## or
+# ATT:   {evex}  orq    $123, %r9
+# INTEL: {evex}  or     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xc9,0x7b
+
+# ATT:   orq    $123, %r9, %r10
+# INTEL: or     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xc9,0x7b
+
+# ATT:   {nf} orq $123, %r9
+# INTEL: {nf} or  r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xc9,0x7b
+
+# ATT:   {nf} orq $123, %r9, %r10
+# INTEL: {nf} or  r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xc9,0x7b
+
+## xor
+# ATT:   {evex}  xorq    $123, %r9
+# INTEL: {evex}  xor     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xf1,0x7b
+
+# ATT:   xorq    $123, %r9, %r10
+# INTEL: xor     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xf1,0x7b
+
+# ATT:   {nf} xorq $123, %r9
+# INTEL: {nf} xor  r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xf1,0x7b
+
+# ATT:   {nf} xorq $123, %r9, %r10
+# INTEL: {nf} xor  r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xf1,0x7b

diff  --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 21c5e3297b23f6..294923b250eea8 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -268,6 +268,7 @@ static inline bool inheritsFrom(InstructionContext child,
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ));
   case IC_EVEX_W:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W)) ||
+           inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W));
   case IC_EVEX_W_XS:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS)) ||
@@ -454,6 +455,7 @@ static inline bool inheritsFrom(InstructionContext child,
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ_B));
   case IC_EVEX_W_B:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_B)) ||
+           inheritsFrom(child, IC_EVEX_W_OPSIZE_B) ||
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_B));
   case IC_EVEX_W_XS_B:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_B)) ||