[llvm] 911b960 - PPC: Custom lower ppcf128 is_fpclass if is_fpclass is custom (#105540)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 29 03:01:57 PDT 2024
Author: Matt Arsenault
Date: 2024-08-29T14:01:54+04:00
New Revision: 911b96058a94a10a3897a56af703992c4509965b
URL: https://github.com/llvm/llvm-project/commit/911b96058a94a10a3897a56af703992c4509965b
DIFF: https://github.com/llvm/llvm-project/commit/911b96058a94a10a3897a56af703992c4509965b.diff
LOG: PPC: Custom lower ppcf128 is_fpclass if is_fpclass is custom (#105540)
Unfortunately expandIS_FPCLASS is called directly in SelectionDAGBuilder
depending on whether IS_FPCLASS is custom or not. This helps avoid ppc test
regressions in a future patch where the custom lowering would be bypassed.
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 83772200ade5c7..8a0858e2462520 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1221,6 +1221,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::IS_FPCLASS, MVT::f32, Custom);
setOperationAction(ISD::IS_FPCLASS, MVT::f64, Custom);
setOperationAction(ISD::IS_FPCLASS, MVT::f128, Custom);
+ setOperationAction(ISD::IS_FPCLASS, MVT::ppcf128, Custom);
}
// 128 bit shifts can be accomplished via 3 instructions for SHL and
@@ -11479,6 +11480,12 @@ SDValue PPCTargetLowering::LowerIS_FPCLASS(SDValue Op,
uint64_t RHSC = Op.getConstantOperandVal(1);
SDLoc Dl(Op);
FPClassTest Category = static_cast<FPClassTest>(RHSC);
+ if (LHS.getValueType() == MVT::ppcf128) {
+ // The higher part determines the value class.
+ LHS = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::f64, LHS,
+ DAG.getConstant(1, Dl, MVT::i32));
+ }
+
return getDataClassTest(LHS, Category, Dl, DAG, Subtarget);
}
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