[llvm] [X86Disassembler] Handle situations when both EVEX.W = 1 and EVEX.pp = 01 (PR #103816)
Freddy Ye via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 29 02:08:58 PDT 2024
https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/103816
>From 1e5d7d7646246a394e27f642fa7df01b0c6f254b Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Wed, 14 Aug 2024 19:35:20 +0800
Subject: [PATCH 1/3] [X86Disassembler] Handle situations when both EVEX.W = 1
and EVEX.pp = 01
---
.../MC/Disassembler/X86/apx/evex-w-opsize.txt | 74 +++++++++++++++++++
llvm/utils/TableGen/X86DisassemblerTables.cpp | 2 +
2 files changed, 76 insertions(+)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
new file mode 100644
index 00000000000000..91287469167b32
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# This test is to check below inherit:
+# IC_EVEX_W --> IC_EVEX_W_OPSIZE
+# IC_EVEX_W_B --> IC_EVEX_W_OPSIZE_B
+
+## adc
+# ATT: {evex} adcq $123, %r9
+# INTEL: {evex} adc r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xd1,0x7b
+
+# ATT: adcq $123, %r9, %r10
+# INTEL: adc r10, r9, 123
+0x62,0xd4,0xac,0x18,0x83,0xd1,0x7b
+
+## add
+# ATT: {evex} addq $123, %r9
+# INTEL: {evex} add r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xc1,0x7b
+
+# ATT: addq $123, %r9, %r10
+# INTEL: add r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xc1,0x7b
+
+## sbb
+# ATT: {evex} sbbq $123, %r9
+# INTEL: {evex} sbb r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xd9,0x7b
+
+# ATT: sbbq $123, %r9, %r10
+# INTEL: sbb r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xd9,0x7b
+
+## sub
+# ATT: {evex} subq $123, %r9
+# INTEL: {evex} sub r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xe9,0x7b
+
+# ATT: subq $123, %r9, %r10
+# INTEL: sub r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xe9,0x7b
+
+## imul
+# ATT: {evex} imulq $123, %r9, %r10
+# INTEL: {evex} imul r10, r9, 123
+0x62,0x54,0xfd,0x08,0x6b,0xd1,0x7b
+
+## and
+# ATT: {evex} andq $123, %r9
+# INTEL: {evex} and r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xe1,0x7b
+
+# ATT: andq $123, %r9, %r10
+# INTEL: and r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xe1,0x7b
+
+## or
+# ATT: {evex} orq $123, %r9
+# INTEL: {evex} or r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xc9,0x7b
+
+# ATT: orq $123, %r9, %r10
+# INTEL: or r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xc9,0x7b
+
+## xor
+# ATT: {evex} xorq $123, %r9
+# INTEL: {evex} xor r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xf1,0x7b
+
+# ATT: xorq $123, %r9, %r10
+# INTEL: xor r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xf1,0x7b
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 21c5e3297b23f6..294923b250eea8 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -268,6 +268,7 @@ static inline bool inheritsFrom(InstructionContext child,
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ));
case IC_EVEX_W:
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W)) ||
+ inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W));
case IC_EVEX_W_XS:
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS)) ||
@@ -454,6 +455,7 @@ static inline bool inheritsFrom(InstructionContext child,
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ_B));
case IC_EVEX_W_B:
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_B)) ||
+ inheritsFrom(child, IC_EVEX_W_OPSIZE_B) ||
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_B));
case IC_EVEX_W_XS_B:
return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_B)) ||
>From 7adaff022d2ef3f9dc1c52452e557add2a48f367 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 29 Aug 2024 17:07:20 +0800
Subject: [PATCH 2/3] address comments.
---
.../MC/Disassembler/X86/apx/evex-w-opsize.txt | 46 ++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
index 91287469167b32..5871f9397aba80 100644
--- a/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
@@ -1,7 +1,7 @@
# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
-# This test is to check below inherit:
+# This test is to check below inherit and other situations EVEX_W and EVEX_OPSIZE both set:
# IC_EVEX_W --> IC_EVEX_W_OPSIZE
# IC_EVEX_W_B --> IC_EVEX_W_OPSIZE_B
@@ -23,6 +23,14 @@
# INTEL: add r10, r9, 123
0x62,0xd4,0xad,0x18,0x83,0xc1,0x7b
+# ATT: {nf} addq $123, %r9
+# INTEL: {nf} add r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xc1,0x7b
+
+# ATT: {nf} addq $123, %r9, %r10
+# INTEL: {nf} add r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xc1,0x7b
+
## sbb
# ATT: {evex} sbbq $123, %r9
# INTEL: {evex} sbb r9, 123
@@ -41,11 +49,23 @@
# INTEL: sub r10, r9, 123
0x62,0xd4,0xad,0x18,0x83,0xe9,0x7b
+# ATT: {nf} subq $123, %r9
+# INTEL: {nf} sub r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xe9,0x7b
+
+# ATT: {nf} subq $123, %r9, %r10
+# INTEL: {nf} sub r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xe9,0x7b
+
## imul
# ATT: {evex} imulq $123, %r9, %r10
# INTEL: {evex} imul r10, r9, 123
0x62,0x54,0xfd,0x08,0x6b,0xd1,0x7b
+# ATT: {nf} imulq $123, %r9, %r10
+# INTEL: {nf} imul r10, r9, 123
+0x62,0x54,0xfd,0x0c,0x6b,0xd1,0x7b
+
## and
# ATT: {evex} andq $123, %r9
# INTEL: {evex} and r9, 123
@@ -55,6 +75,14 @@
# INTEL: and r10, r9, 123
0x62,0xd4,0xad,0x18,0x83,0xe1,0x7b
+# ATT: {nf} andq $123, %r9
+# INTEL: {nf} and r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xe1,0x7b
+
+# ATT: {nf} andq $123, %r9, %r10
+# INTEL: {nf} and r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xe1,0x7b
+
## or
# ATT: {evex} orq $123, %r9
# INTEL: {evex} or r9, 123
@@ -64,6 +92,14 @@
# INTEL: or r10, r9, 123
0x62,0xd4,0xad,0x18,0x83,0xc9,0x7b
+# ATT: {nf} orq $123, %r9
+# INTEL: {nf} or r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xc9,0x7b
+
+# ATT: {nf} orq $123, %r9, %r10
+# INTEL: {nf} or r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xc9,0x7b
+
## xor
# ATT: {evex} xorq $123, %r9
# INTEL: {evex} xor r9, 123
@@ -72,3 +108,11 @@
# ATT: xorq $123, %r9, %r10
# INTEL: xor r10, r9, 123
0x62,0xd4,0xad,0x18,0x83,0xf1,0x7b
+
+# ATT: {nf} xorq $123, %r9
+# INTEL: {nf} xor r9, 123
+0x62,0xd4,0xfd,0x0c,0x83,0xf1,0x7b
+
+# ATT: {nf} xorq $123, %r9, %r10
+# INTEL: {nf} xor r10, r9, 123
+0x62,0xd4,0xad,0x1c,0x83,0xf1,0x7b
>From fc5a88b81c3fb0d964aadbe9922fd59b60015f30 Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Thu, 29 Aug 2024 17:08:45 +0800
Subject: [PATCH 3/3] address comments.
---
llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
index 5871f9397aba80..e2400b366ef62c 100644
--- a/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
@@ -1,9 +1,7 @@
# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
-# This test is to check below inherit and other situations EVEX_W and EVEX_OPSIZE both set:
-# IC_EVEX_W --> IC_EVEX_W_OPSIZE
-# IC_EVEX_W_B --> IC_EVEX_W_OPSIZE_B
+## This test is to check OSIZE=64b when EVEX.W=1 and EVEX.pp = 01.
## adc
# ATT: {evex} adcq $123, %r9
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