[llvm] [RISCV] Model dest EEW and fix peepholes not checking EEW (PR #105945)

[Luke Lau via llvm-commits]

================
@@ -201,21 +201,24 @@ let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,
   defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR,    VR,    FPR32>, Sched<[]>;
 }
 
-let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod" in {
+let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvqmaccdod",
+    DestEEW = EEWSEWx4 in {
   def VQMACCU_2x8x2  : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;
   def VQMACC_2x8x2   : CustomSiFiveVMACC<0b101101, OPMVV, "sf.vqmacc.2x8x2">;
   def VQMACCUS_2x8x2 : CustomSiFiveVMACC<0b101110, OPMVV, "sf.vqmaccus.2x8x2">;
   def VQMACCSU_2x8x2 : CustomSiFiveVMACC<0b101111, OPMVV, "sf.vqmaccsu.2x8x2">;
 }
 
-let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq" in {
+let Predicates = [HasVendorXSfvqmaccqoq], DecoderNamespace = "XSfvqmaccqoq",
+    DestEEW = EEWSEWx4 in {
----------------
lukel97 wrote:

Given what @preames has said, I don't think we need the EMULs to match. 

For tryToReduceVL, we replace the source's VL with a smaller VL, which gives the same result regardless of the source's EMUL.

For foldVMV_V_V, we replace a vmv.v.v with a source with the same EEW and a less than or equal VL. 

At EMUL >= m1, the EMULs will match because the register classes will need to match. 

We might have mismatched EMULs when < m1, but even if we increase or decrease the resulting LMUL the result is the same:

```
%add:vr = PseudoVADD_VV_MF8 %pt, %1, %2, 2/*VL*/, 4 /*SEW*/, 0
%vmv:vr = PseudoVMV_V_V_MF4 %pt, %add, 3/*VL*/, 4 /*SEW*/, 0
->
%vmv:vr = PseudoVADD_VV_MF8 %pt, %1, %2, 2 /*VL*/, 4 /*SEW*/, 0

%add:vr = PseudoVADD_VV_MF4 %pt, %1, %2, 2/*VL*/, 4 /*SEW*/, 0
%vmv:vr = PseudoVMV_V_V_MF8 %pt, %add, 3/*VL*/, 4 /*SEW*/, 0
->
%vmv:vr = PseudoVADD_VV_MF4 %pt, %1, %2, 2 /*VL*/, 4 /*SEW*/, 0
```

Because the specification mandates that the tail includes the entire vector register.

> When LMUL < 1, the tail includes the elements past VLMAX that are held in the same vector register.

https://github.com/llvm/llvm-project/pull/105945