[llvm] [llvm][Mips] Bail on underaligned loads/stores in FastISel. (PR #106231)

[Alex Rønne Petersen via llvm-commits]

https://github.com/alexrp updated https://github.com/llvm/llvm-project/pull/106231

>From caa9db1998aa55c038323bf00af7da731af9649c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex at alexrp.com>
Date: Tue, 27 Aug 2024 16:27:39 +0200
Subject: [PATCH] [llvm][Mips] Bail on underaligned loads/stores in FastISel.

---
 llvm/lib/Target/Mips/MipsFastISel.cpp         | 28 +++++++++++++------
 .../Mips/Fast-ISel/underaligned-load-store.ll | 23 +++++++++++++++
 2 files changed, 43 insertions(+), 8 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/Fast-ISel/underaligned-load-store.ll

diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 7d8278c8ca3cf5..5ff9429bcec2e4 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -881,38 +881,50 @@ bool MipsFastISel::selectLogicalOp(const Instruction *I) {
 }
 
 bool MipsFastISel::selectLoad(const Instruction *I) {
+  const LoadInst *LI = cast<LoadInst>(I);
+
   // Atomic loads need special handling.
-  if (cast<LoadInst>(I)->isAtomic())
+  if (LI->isAtomic())
     return false;
 
   // Verify we have a legal type before going any further.
   MVT VT;
-  if (!isLoadTypeLegal(I->getType(), VT))
+  if (!isLoadTypeLegal(LI->getType(), VT))
+    return false;
+
+  // Underaligned loads need special handling.
+  if (LI->getAlign() < VT.getFixedSizeInBits() / 8)
     return false;
 
   // See if we can handle this address.
   Address Addr;
-  if (!computeAddress(I->getOperand(0), Addr))
+  if (!computeAddress(LI->getOperand(0), Addr))
     return false;
 
   unsigned ResultReg;
   if (!emitLoad(VT, ResultReg, Addr))
     return false;
-  updateValueMap(I, ResultReg);
+  updateValueMap(LI, ResultReg);
   return true;
 }
 
 bool MipsFastISel::selectStore(const Instruction *I) {
-  Value *Op0 = I->getOperand(0);
+  const StoreInst *SI = cast<StoreInst>(I);
+
+  Value *Op0 = SI->getOperand(0);
   unsigned SrcReg = 0;
 
   // Atomic stores need special handling.
-  if (cast<StoreInst>(I)->isAtomic())
+  if (SI->isAtomic())
     return false;
 
   // Verify we have a legal type before going any further.
   MVT VT;
-  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
+  if (!isLoadTypeLegal(SI->getOperand(0)->getType(), VT))
+    return false;
+
+  // Underaligned stores need special handling.
+  if (SI->getAlign() < VT.getFixedSizeInBits() / 8)
     return false;
 
   // Get the value to be stored into a register.
@@ -922,7 +934,7 @@ bool MipsFastISel::selectStore(const Instruction *I) {
 
   // See if we can handle this address.
   Address Addr;
-  if (!computeAddress(I->getOperand(1), Addr))
+  if (!computeAddress(SI->getOperand(1), Addr))
     return false;
 
   if (!emitStore(VT, SrcReg, Addr))
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/underaligned-load-store.ll b/llvm/test/CodeGen/Mips/Fast-ISel/underaligned-load-store.ll
new file mode 100644
index 00000000000000..6e299c724c4ee7
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/underaligned-load-store.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march mips -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS
+
+ at var = external global i32, align 1
+
+; FastISel should bail on the underaligned load and store.
+define dso_local ccc i32 @__start() {
+; MIPS-LABEL: __start:
+; MIPS:       # %bb.0:
+; MIPS-NEXT:    lui $2, %hi(_gp_disp)
+; MIPS-NEXT:    addiu $2, $2, %lo(_gp_disp)
+; MIPS-NEXT:    addu $1, $2, $25
+; MIPS-NEXT:    lw $1, %got(var)($1)
+; MIPS-NEXT:    lwl $2, 0($1)
+; MIPS-NEXT:    lwr $2, 3($1)
+; MIPS-NEXT:    addiu $3, $zero, 42
+; MIPS-NEXT:    swl $3, 0($1)
+; MIPS-NEXT:    jr $ra
+; MIPS-NEXT:    swr $3, 3($1)
+    %1 = load i32, ptr @var, align 1
+    store i32 42, ptr @var, align 1
+    ret i32 %1
+}