[llvm] 62c5de3 - [RISCV] Fix a place that convert an immediate to MCRegister and back to immediate.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-08-28T22:35:24-07:00
New Revision: 62c5de36e8a523cc81950a782a4b6182393681c4

URL: https://github.com/llvm/llvm-project/commit/62c5de36e8a523cc81950a782a4b6182393681c4
DIFF: https://github.com/llvm/llvm-project/commit/62c5de36e8a523cc81950a782a4b6182393681c4.diff

LOG: [RISCV] Fix a place that convert an immediate to MCRegister and back to immediate.

This dropped the upper 32 bits of the immediate, but I'm not sure
it is ever non-zero.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 0863345b0c6dc6..75323632dd5333 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -172,7 +172,7 @@ void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
   const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
   MCRegister Link = MI.getOperand(0).getReg();
   MCRegister Dest = MI.getOperand(1).getReg();
-  MCRegister Imm = MI.getOperand(2).getImm();
+  int64_t Imm = MI.getOperand(2).getImm();
   Fixups.push_back(MCFixup::create(
       0, Expr, MCFixupKind(RISCV::fixup_riscv_tlsdesc_call), MI.getLoc()));
   MCInst Call =