[llvm] [X86][dec] Handle EVEX.W = 1 and EVEX.pp = 01 (PR #103816)

[Freddy Ye via llvm-commits]

https://github.com/FreddyLeaf updated https://github.com/llvm/llvm-project/pull/103816

>From 1e5d7d7646246a394e27f642fa7df01b0c6f254b Mon Sep 17 00:00:00 2001
From: Freddy Ye <freddy.ye at intel.com>
Date: Wed, 14 Aug 2024 19:35:20 +0800
Subject: [PATCH] [X86Disassembler] Handle situations when both EVEX.W = 1 and
 EVEX.pp = 01

---
 .../MC/Disassembler/X86/apx/evex-w-opsize.txt | 74 +++++++++++++++++++
 llvm/utils/TableGen/X86DisassemblerTables.cpp |  2 +
 2 files changed, 76 insertions(+)
 create mode 100644 llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt

diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
new file mode 100644
index 00000000000000..91287469167b32
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/evex-w-opsize.txt
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# This test is to check below inherit:
+# IC_EVEX_W       -->    IC_EVEX_W_OPSIZE
+# IC_EVEX_W_B     -->    IC_EVEX_W_OPSIZE_B
+
+## adc
+# ATT:   {evex}  adcq    $123, %r9
+# INTEL: {evex}  adc     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xd1,0x7b
+
+# ATT:   adcq    $123, %r9, %r10
+# INTEL: adc     r10, r9, 123
+0x62,0xd4,0xac,0x18,0x83,0xd1,0x7b
+
+## add
+# ATT:   {evex}  addq    $123, %r9
+# INTEL: {evex}  add     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xc1,0x7b
+
+# ATT:   addq    $123, %r9, %r10
+# INTEL: add     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xc1,0x7b
+
+## sbb
+# ATT:   {evex}  sbbq    $123, %r9
+# INTEL: {evex}  sbb     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xd9,0x7b
+
+# ATT:   sbbq    $123, %r9, %r10
+# INTEL: sbb     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xd9,0x7b
+
+## sub
+# ATT:   {evex}  subq    $123, %r9
+# INTEL: {evex}  sub     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xe9,0x7b
+
+# ATT:   subq    $123, %r9, %r10
+# INTEL: sub     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xe9,0x7b
+
+## imul
+# ATT:   {evex}  imulq    $123, %r9, %r10
+# INTEL: {evex}  imul     r10, r9, 123
+0x62,0x54,0xfd,0x08,0x6b,0xd1,0x7b
+
+## and
+# ATT:   {evex}  andq    $123, %r9
+# INTEL: {evex}  and     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xe1,0x7b
+
+# ATT:   andq    $123, %r9, %r10
+# INTEL: and     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xe1,0x7b
+
+## or
+# ATT:   {evex}  orq    $123, %r9
+# INTEL: {evex}  or     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xc9,0x7b
+
+# ATT:   orq    $123, %r9, %r10
+# INTEL: or     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xc9,0x7b
+
+## xor
+# ATT:   {evex}  xorq    $123, %r9
+# INTEL: {evex}  xor     r9, 123
+0x62,0xd4,0xfd,0x08,0x83,0xf1,0x7b
+
+# ATT:   xorq    $123, %r9, %r10
+# INTEL: xor     r10, r9, 123
+0x62,0xd4,0xad,0x18,0x83,0xf1,0x7b
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
index 21c5e3297b23f6..294923b250eea8 100644
--- a/llvm/utils/TableGen/X86DisassemblerTables.cpp
+++ b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -268,6 +268,7 @@ static inline bool inheritsFrom(InstructionContext child,
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ));
   case IC_EVEX_W:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W)) ||
+           inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W));
   case IC_EVEX_W_XS:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS)) ||
@@ -454,6 +455,7 @@ static inline bool inheritsFrom(InstructionContext child,
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE_KZ_B));
   case IC_EVEX_W_B:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_B)) ||
+           inheritsFrom(child, IC_EVEX_W_OPSIZE_B) ||
            (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_W_B));
   case IC_EVEX_W_XS_B:
     return (VEX_LIG && inheritsFrom(child, IC_EVEX_L_W_XS_B)) ||