[llvm] Revert "[CodeGen] Use MachineInstr::{all_uses, all_defs} (NFC)" (PR #106451)

[Vitaly Buka via llvm-commits]

https://github.com/vitalybuka created https://github.com/llvm/llvm-project/pull/106451

Reverts llvm/llvm-project#106404

Breaks:
https://lab.llvm.org/buildbot/#/builders/169/builds/2590
https://lab.llvm.org/buildbot/#/builders/164/builds/2454

>From 1740035264c3326d7dabee0682dd3802bc4384d7 Mon Sep 17 00:00:00 2001
From: Vitaly Buka <vitalybuka at gmail.com>
Date: Wed, 28 Aug 2024 13:35:28 -0700
Subject: [PATCH] Revert "[CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC)
 (#106404)"

This reverts commit a4989cd603b8e8185e35e3c2b7b48b422d4898be.
---
 .../CodeGen/MachineConvergenceVerifier.cpp    |  4 +++-
 llvm/lib/CodeGen/MachineInstr.cpp             | 20 ++++++++++++-------
 llvm/lib/CodeGen/RegAllocFast.cpp             |  4 +++-
 3 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp b/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
index ac6b04a202c533..3d3c55faa82465 100644
--- a/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
@@ -51,7 +51,9 @@ GenericConvergenceVerifier<MachineSSAContext>::findAndCheckConvergenceTokenUsed(
   const MachineRegisterInfo &MRI = Context.getFunction()->getRegInfo();
   const MachineInstr *TokenDef = nullptr;
 
-  for (const MachineOperand &MO : MI.all_uses()) {
+  for (const MachineOperand &MO : MI.operands()) {
+    if (!MO.isReg() || !MO.isUse())
+      continue;
     Register OpReg = MO.getReg();
     if (!OpReg.isVirtual())
       continue;
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 7f81aeb545d328..f21910ee3a444a 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1041,9 +1041,10 @@ unsigned MachineInstr::getBundleSize() const {
 /// Returns true if the MachineInstr has an implicit-use operand of exactly
 /// the given register (not considering sub/super-registers).
 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
-  for (const MachineOperand &MO : all_uses())
-    if (MO.isImplicit() && MO.getReg() == Reg)
+  for (const MachineOperand &MO : operands()) {
+    if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
       return true;
+  }
   return false;
 }
 
@@ -1263,8 +1264,10 @@ unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
 /// clearKillInfo - Clears kill flags on all operands.
 ///
 void MachineInstr::clearKillInfo() {
-  for (MachineOperand &MO : all_uses())
-    MO.setIsKill(false);
+  for (MachineOperand &MO : operands()) {
+    if (MO.isReg() && MO.isUse())
+      MO.setIsKill(false);
+  }
 }
 
 void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
@@ -1546,9 +1549,12 @@ bool MachineInstr::isLoadFoldBarrier() const {
 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
 ///
 bool MachineInstr::allDefsAreDead() const {
-  for (const MachineOperand &MO : all_defs())
+  for (const MachineOperand &MO : operands()) {
+    if (!MO.isReg() || MO.isUse())
+      continue;
     if (!MO.isDead())
       return false;
+  }
   return true;
 }
 
@@ -2057,8 +2063,8 @@ void MachineInstr::clearRegisterKills(Register Reg,
                                       const TargetRegisterInfo *RegInfo) {
   if (!Reg.isPhysical())
     RegInfo = nullptr;
-  for (MachineOperand &MO : all_uses()) {
-    if (!MO.isKill())
+  for (MachineOperand &MO : operands()) {
+    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
       continue;
     Register OpReg = MO.getReg();
     if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index a0a8a8897af7f2..6babd5a3f1f96f 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1563,7 +1563,9 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
   bool ReArrangedImplicitMOs = true;
   while (ReArrangedImplicitMOs) {
     ReArrangedImplicitMOs = false;
-    for (MachineOperand &MO : MI.all_uses()) {
+    for (MachineOperand &MO : MI.operands()) {
+      if (!MO.isReg() || !MO.isUse())
+        continue;
       Register Reg = MO.getReg();
       if (!Reg.isVirtual() || !shouldAllocateRegister(Reg))
         continue;