[llvm] a4989cd - [CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC) (#106404)

[via llvm-commits]

Author: Kazu Hirata
Date: 2024-08-28T11:07:31-07:00
New Revision: a4989cd603b8e8185e35e3c2b7b48b422d4898be

URL: https://github.com/llvm/llvm-project/commit/a4989cd603b8e8185e35e3c2b7b48b422d4898be
DIFF: https://github.com/llvm/llvm-project/commit/a4989cd603b8e8185e35e3c2b7b48b422d4898be.diff

LOG: [CodeGen] Use MachineInstr::{all_uses,all_defs} (NFC) (#106404)

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
    llvm/lib/CodeGen/MachineInstr.cpp
    llvm/lib/CodeGen/RegAllocFast.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp b/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
index 3d3c55faa82465..ac6b04a202c533 100644
--- a/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineConvergenceVerifier.cpp
@@ -51,9 +51,7 @@ GenericConvergenceVerifier<MachineSSAContext>::findAndCheckConvergenceTokenUsed(
   const MachineRegisterInfo &MRI = Context.getFunction()->getRegInfo();
   const MachineInstr *TokenDef = nullptr;
 
-  for (const MachineOperand &MO : MI.operands()) {
-    if (!MO.isReg() || !MO.isUse())
-      continue;
+  for (const MachineOperand &MO : MI.all_uses()) {
     Register OpReg = MO.getReg();
     if (!OpReg.isVirtual())
       continue;

diff  --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index f21910ee3a444a..7f81aeb545d328 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1041,10 +1041,9 @@ unsigned MachineInstr::getBundleSize() const {
 /// Returns true if the MachineInstr has an implicit-use operand of exactly
 /// the given register (not considering sub/super-registers).
 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
-  for (const MachineOperand &MO : operands()) {
-    if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
+  for (const MachineOperand &MO : all_uses())
+    if (MO.isImplicit() && MO.getReg() == Reg)
       return true;
-  }
   return false;
 }
 
@@ -1264,10 +1263,8 @@ unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
 /// clearKillInfo - Clears kill flags on all operands.
 ///
 void MachineInstr::clearKillInfo() {
-  for (MachineOperand &MO : operands()) {
-    if (MO.isReg() && MO.isUse())
-      MO.setIsKill(false);
-  }
+  for (MachineOperand &MO : all_uses())
+    MO.setIsKill(false);
 }
 
 void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
@@ -1549,12 +1546,9 @@ bool MachineInstr::isLoadFoldBarrier() const {
 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
 ///
 bool MachineInstr::allDefsAreDead() const {
-  for (const MachineOperand &MO : operands()) {
-    if (!MO.isReg() || MO.isUse())
-      continue;
+  for (const MachineOperand &MO : all_defs())
     if (!MO.isDead())
       return false;
-  }
   return true;
 }
 
@@ -2063,8 +2057,8 @@ void MachineInstr::clearRegisterKills(Register Reg,
                                       const TargetRegisterInfo *RegInfo) {
   if (!Reg.isPhysical())
     RegInfo = nullptr;
-  for (MachineOperand &MO : operands()) {
-    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
+  for (MachineOperand &MO : all_uses()) {
+    if (!MO.isKill())
       continue;
     Register OpReg = MO.getReg();
     if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)

diff  --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index 6babd5a3f1f96f..a0a8a8897af7f2 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1563,9 +1563,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
   bool ReArrangedImplicitMOs = true;
   while (ReArrangedImplicitMOs) {
     ReArrangedImplicitMOs = false;
-    for (MachineOperand &MO : MI.operands()) {
-      if (!MO.isReg() || !MO.isUse())
-        continue;
+    for (MachineOperand &MO : MI.all_uses()) {
       Register Reg = MO.getReg();
       if (!Reg.isVirtual() || !shouldAllocateRegister(Reg))
         continue;