[llvm] [Attributor] Fix an issue that could potentially cause `AccessList` and `OffsetBins` out of sync (PR #106187)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 28 10:57:43 PDT 2024
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/106187
>From 1a231923168ae27e1d8b29ba0f8d4ab95c28debf Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Tue, 27 Aug 2024 01:29:19 -0400
Subject: [PATCH] [Attributor] Fix an issue that could potentially cause
`AccessList` and `OffsetBins` out of sync
The implementation of `AAPointerInfo::RangeList::set_difference` doesn't
consider the case where two ranges have the same offset but different sizes.
This could causes `AccessList` and `OffsetBins` out of sync because a range has
been already updated in `AccessList` but missing in `ToRemove`.
I do have a reproducer but the reproducer itself is 248kb. `llvm-reduce` can't
further reduce it. Not sure how I can make a smaller reproducer.
Fix SWDEV-479757.
---
llvm/include/llvm/Transforms/IPO/Attributor.h | 8 +-
...butor-accesslist-offsetbins-out-of-sync.ll | 95 +++++++++++++++++++
2 files changed, 101 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h
index 718cf704cbdf1a..57aea2c6897e8c 100644
--- a/llvm/include/llvm/Transforms/IPO/Attributor.h
+++ b/llvm/include/llvm/Transforms/IPO/Attributor.h
@@ -5817,8 +5817,12 @@ struct AAPointerInfo : public AbstractAttribute {
/// Copy ranges from \p L that are not in \p R, into \p D.
static void set_difference(const RangeList &L, const RangeList &R,
RangeList &D) {
- std::set_difference(L.begin(), L.end(), R.begin(), R.end(),
- std::back_inserter(D), RangeTy::OffsetLessThan);
+ std::set_difference(
+ L.begin(), L.end(), R.begin(), R.end(), std::back_inserter(D),
+ [](const RangeTy &L, const RangeTy &R) {
+ return (L.Offset < R.Offset) ||
+ ((L.Offset == R.Offset) && (L.Size != R.Size));
+ });
}
unsigned size() const { return Ranges.size(); }
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
new file mode 100644
index 00000000000000..8276af70fb27c6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-attributor-accesslist-offsetbins-out-of-sync.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes='amdgpu-attributor' %s -o - | FileCheck %s
+
+%struct.ShaderClosure = type { <3 x float>, i32, float, <3 x float>, [10 x float], [8 x i8] }
+%struct.ShaderData = type { <3 x float>, <3 x float>, <3 x float>, <3 x float>, i32, i32, i32, i32, i32, float, float, i32, i32, float, float, %struct.differential3, %struct.differential3, %struct.differential, %struct.differential, <3 x float>, <3 x float>, <3 x float>, %struct.differential3, i32, i32, i32, float, <3 x float>, <3 x float>, <3 x float>, [64 x %struct.ShaderClosure] }
+%struct.differential = type { float, float }
+%struct.differential3 = type { <3 x float>, <3 x float> }
+
+define internal fastcc void @foo(ptr %kg) {
+; CHECK-LABEL: define internal fastcc void @foo(
+; CHECK-SAME: ptr [[KG:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CLOSURE_I25_I:%.*]] = getelementptr i8, ptr [[KG]], i64 336
+; CHECK-NEXT: [[NUM_CLOSURE_I26_I:%.*]] = getelementptr i8, ptr [[KG]], i64 276
+; CHECK-NEXT: br label %[[WHILE_COND:.*]]
+; CHECK: [[WHILE_COND]]:
+; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[KG]] to ptr addrspace(5)
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[TMP0]], align 4
+; CHECK-NEXT: [[IDXPROM_I:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: switch i32 0, label %[[SW_BB92:.*]] [
+; CHECK-NEXT: i32 1, label %[[SW_BB92]]
+; CHECK-NEXT: i32 0, label %[[SUBD_TRIANGLE_PATCH_EXIT_I_I35:.*]]
+; CHECK-NEXT: ]
+; CHECK: [[SUBD_TRIANGLE_PATCH_EXIT_I_I35]]:
+; CHECK-NEXT: [[ARRAYIDX_I27_I:%.*]] = getelementptr float, ptr [[KG]], i64 [[IDXPROM_I]]
+; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[ARRAYIDX_I27_I]] to ptr addrspace(5)
+; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(5) [[TMP2]], align 4
+; CHECK-NEXT: br label %[[WHILE_COND]]
+; CHECK: [[SW_BB92]]:
+; CHECK-NEXT: [[INSERT:%.*]] = insertelement <3 x i32> zeroinitializer, i32 [[TMP1]], i64 0
+; CHECK-NEXT: [[SPLAT_SPLATINSERT_I:%.*]] = bitcast <3 x i32> [[INSERT]] to <3 x float>
+; CHECK-NEXT: [[SHFL:%.*]] = shufflevector <3 x float> [[SPLAT_SPLATINSERT_I]], <3 x float> zeroinitializer, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr [[NUM_CLOSURE_I26_I]] to ptr addrspace(5)
+; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4
+; CHECK-NEXT: [[IDXPROM_I27_I:%.*]] = sext i32 [[LOAD]] to i64
+; CHECK-NEXT: [[ARRAYIDX_I28_I:%.*]] = getelementptr [64 x %struct.ShaderClosure], ptr [[CLOSURE_I25_I]], i64 0, i64 [[IDXPROM_I27_I]]
+; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ARRAYIDX_I28_I]] to ptr addrspace(5)
+; CHECK-NEXT: store <4 x float> [[SHFL]], ptr addrspace(5) [[TMP4]], align 16
+; CHECK-NEXT: [[INC_I30_I:%.*]] = or i32 [[LOAD]], 1
+; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[NUM_CLOSURE_I26_I]] to ptr addrspace(5)
+; CHECK-NEXT: store i32 [[INC_I30_I]], ptr addrspace(5) [[TMP5]], align 4
+; CHECK-NEXT: br label %[[WHILE_COND]]
+;
+entry:
+ %closure.i25.i = getelementptr i8, ptr %kg, i64 336
+ %num_closure.i26.i = getelementptr i8, ptr %kg, i64 276
+ br label %while.cond
+
+while.cond:
+ %0 = load i32, ptr %kg, align 4
+ %idxprom.i = zext i32 %0 to i64
+ switch i32 0, label %sw.bb92 [
+ i32 1, label %sw.bb92
+ i32 0, label %subd_triangle_patch.exit.i.i35
+ ]
+
+subd_triangle_patch.exit.i.i35:
+ %arrayidx.i27.i = getelementptr float, ptr %kg, i64 %idxprom.i
+ store float 0.000000e+00, ptr %arrayidx.i27.i, align 4
+ br label %while.cond
+
+sw.bb92:
+ %insert = insertelement <3 x i32> zeroinitializer, i32 %0, i64 0
+ %splat.splatinsert.i = bitcast <3 x i32> %insert to <3 x float>
+ %shfl = shufflevector <3 x float> %splat.splatinsert.i, <3 x float> zeroinitializer, <4 x i32> zeroinitializer
+ %load = load i32, ptr %num_closure.i26.i, align 4
+ %idxprom.i27.i = sext i32 %load to i64
+ %arrayidx.i28.i = getelementptr [64 x %struct.ShaderClosure], ptr %closure.i25.i, i64 0, i64 %idxprom.i27.i
+ store <4 x float> %shfl, ptr %arrayidx.i28.i, align 16
+ %inc.i30.i = or i32 %load, 1
+ store i32 %inc.i30.i, ptr %num_closure.i26.i, align 4
+ br label %while.cond
+}
+
+define amdgpu_kernel void @kernel() #0 {
+; CHECK-LABEL: define amdgpu_kernel void @kernel(
+; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[SD_I1111111111:%.*]] = alloca [0 x [0 x [0 x [0 x [0 x [0 x [0 x [0 x [0 x %struct.ShaderData]]]]]]]]], i32 0, align 16, addrspace(5)
+; CHECK-NEXT: [[KGLOBALS_ASCAST1:%.*]] = addrspacecast ptr addrspace(5) [[SD_I1111111111]] to ptr
+; CHECK-NEXT: [[NUM_CLOSURE_I_I:%.*]] = getelementptr i8, ptr addrspace(5) [[SD_I1111111111]], i32 276
+; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr addrspace(5) [[NUM_CLOSURE_I_I]], align 4
+; CHECK-NEXT: call fastcc void @foo(ptr [[KGLOBALS_ASCAST1]])
+; CHECK-NEXT: ret void
+;
+entry:
+ %sd.i1111111111 = alloca [0 x [0 x [0 x [0 x [0 x [0 x [0 x [0 x [0 x %struct.ShaderData]]]]]]]]], i32 0, align 16, addrspace(5)
+ %kglobals.ascast1 = addrspacecast ptr addrspace(5) %sd.i1111111111 to ptr
+ %num_closure.i.i = getelementptr i8, ptr addrspace(5) %sd.i1111111111, i32 276
+ store <2 x i32> zeroinitializer, ptr addrspace(5) %num_closure.i.i, align 4
+ call fastcc void @foo(ptr %kglobals.ascast1)
+ ret void
+}
+
+attributes #0 = { norecurse }
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