[llvm] [AArch64][SelectionDAG] Implement vector splitting for histogram intrinsic (PR #103037)

[Sander de Smalen via llvm-commits]

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@@ -1777,10 +1777,12 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
 
     // Histcnt is SVE2 only
     if (Subtarget->hasSVE2()) {
-      setOperationAction(ISD::EXPERIMENTAL_VECTOR_HISTOGRAM, MVT::Other,
+      setOperationAction(ISD::EXPERIMENTAL_VECTOR_HISTOGRAM, MVT::i8, Promote);
+      setOperationAction(ISD::EXPERIMENTAL_VECTOR_HISTOGRAM, MVT::i16, Promote);
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sdesmalen-arm wrote:

These two `setOperationActions`s are unnecessary, because i8 and i16 are illegal types, so the legalizer will already try to legalize the operation, regardless of this `setOperationAction`.

https://github.com/llvm/llvm-project/pull/103037