[llvm] [AArch64] Prevent generating tbl instruction instead of smull (PR #106375)

[Florian Hahn via llvm-commits]

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@@ -16795,6 +16795,16 @@ bool AArch64TargetLowering::optimizeExtendOrTruncateConversion(
 
       DstTy = TruncDstType;
     }
+
+    // mul(zext(i8), sext) can be transformed into smull(zext, sext) when
+    // destination type is at least i32, which is faster than using tbl
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fhahn wrote:

i32 is not mentioned below, would be good to update the comment to refer to the `SrcWidth * 4` below?

https://github.com/llvm/llvm-project/pull/106375