[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)

[Paul Walker via llvm-commits]

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@@ -21229,6 +21249,101 @@ static SDValue tryCombineWhileLo(SDNode *N,
   return SDValue(N, 0);
 }
 
+SDValue tryLowerPartialReductionToDot(SDNode *N,
+                                      const AArch64Subtarget *Subtarget,
+                                      SelectionDAG &DAG) {
+
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paulwalker-arm wrote:

Please add an asset to verify N is what you expect it to be.

In general you should assume knowledge from `shouldExpandPartialReductionIntrinsic` and should reverify the input types are supported by the following code.

https://github.com/llvm/llvm-project/pull/101010