[llvm] [AArch64] optimise SVE cvt intrinsics with no active lanes (PR #104809)

[Maciej Gabka via llvm-commits]

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@@ -0,0 +1,411 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+target triple = "aarch64-unknown-linux-gnu"
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mgabka wrote:

could you please add at least one case with under/poison value, i.e when the transformation does not take place?

https://github.com/llvm/llvm-project/pull/104809