[llvm] 78505ad - [AMDGPU] Use range-based for loops (NFC) (#106184)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 27 06:46:04 PDT 2024
Author: Kazu Hirata
Date: 2024-08-27T06:46:01-07:00
New Revision: 78505ade2c2e7d4d180e110442e0b074217877c8
URL: https://github.com/llvm/llvm-project/commit/78505ade2c2e7d4d180e110442e0b074217877c8
DIFF: https://github.com/llvm/llvm-project/commit/78505ade2c2e7d4d180e110442e0b074217877c8.diff
LOG: [AMDGPU] Use range-based for loops (NFC) (#106184)
Added:
Modified:
llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp b/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
index de3c06f3a71e28..0fa8d4847931a1 100644
--- a/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
+++ b/llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
@@ -180,11 +180,8 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
MachineBasicBlock::iterator BBEnd) {
const R600RegisterInfo &TRI = TII->getRegisterInfo();
//TODO: change this to defs?
- for (MachineInstr::const_mop_iterator
- MOI = Def->operands_begin(),
- MOE = Def->operands_end(); MOI != MOE; ++MOI) {
- if (!MOI->isReg() || !MOI->isDef() ||
- TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
+ for (MachineOperand &MO : Def->all_defs()) {
+ if (TRI.isPhysRegLiveAcrossClauses(MO.getReg()))
continue;
// Def defines a clause local register, so check that its use will fit
@@ -208,11 +205,11 @@ class R600EmitClauseMarkers : public MachineFunctionPass {
// occur in the same basic block as its definition, because
// it is illegal for the scheduler to schedule them in
//
diff erent blocks.
- if (UseI->readsRegister(MOI->getReg(), &TRI))
+ if (UseI->readsRegister(MO.getReg(), &TRI))
LastUseCount = AluInstCount;
// Exit early if the current use kills the register
- if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
+ if (UseI != Def && UseI->killsRegister(MO.getReg(), &TRI))
break;
}
if (LastUseCount)
diff --git a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
index eded8063feaaa7..a2ce8ee361040d 100644
--- a/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
@@ -350,13 +350,9 @@ void R600SchedStrategy::AssignSlot(MachineInstr* MI, unsigned Slot) {
Register DestReg = MI->getOperand(DstIndex).getReg();
// PressureRegister crashes if an operand is def and used in the same inst
// and we try to constraint its regclass
- for (MachineInstr::mop_iterator It = MI->operands_begin(),
- E = MI->operands_end(); It != E; ++It) {
- MachineOperand &MO = *It;
- if (MO.isReg() && !MO.isDef() &&
- MO.getReg() == DestReg)
+ for (const MachineOperand &MO : MI->all_uses())
+ if (MO.getReg() == DestReg)
return;
- }
// Constrains the regclass of DestReg to assign it to Slot
switch (Slot) {
case 0:
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index eafe20be17d5b9..8ae7f2910ec5a9 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -883,10 +883,8 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
// can be used as the actual source after export patching, so
// we need to treat them like sources and set the EXP_CNT
// score.
- for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
- MachineOperand &DefMO = Inst.getOperand(I);
- if (DefMO.isReg() && DefMO.isDef() &&
- TRI->isVGPR(*MRI, DefMO.getReg())) {
+ for (MachineOperand &DefMO : Inst.all_defs()) {
+ if (TRI->isVGPR(*MRI, DefMO.getReg())) {
setRegScore(
TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)),
EXP_CNT, CurrScore);
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