[llvm] b01c006 - [TII][RISCV] Add renamable bit to copyPhysReg (#91179)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 26 19:08:46 PDT 2024
Author: Piyou Chen
Date: 2024-08-27T10:08:43+08:00
New Revision: b01c006f734a0977a4fd9c7f1a706c8230663739
URL: https://github.com/llvm/llvm-project/commit/b01c006f734a0977a4fd9c7f1a706c8230663739
DIFF: https://github.com/llvm/llvm-project/commit/b01c006f734a0977a4fd9c7f1a706c8230663739.diff
LOG: [TII][RISCV] Add renamable bit to copyPhysReg (#91179)
The renamable flag is useful during MachineCopyPropagation but renamable
flag will be dropped after lowerCopy in some case.
This patch introduces extra arguments to pass the renamable flag to
copyPhysReg.
Added:
llvm/test/CodeGen/RISCV/renamable-copy.mir
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/lib/Target/AMDGPU/R600InstrInfo.h
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/ARC/ARCInstrInfo.cpp
llvm/lib/Target/ARC/ARCInstrInfo.h
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/lib/Target/ARM/Thumb1InstrInfo.h
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.h
llvm/lib/Target/AVR/AVRInstrInfo.cpp
llvm/lib/Target/AVR/AVRInstrInfo.h
llvm/lib/Target/BPF/BPFInstrInfo.cpp
llvm/lib/Target/BPF/BPFInstrInfo.h
llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
llvm/lib/Target/CSKY/CSKYInstrInfo.h
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
llvm/lib/Target/Lanai/LanaiInstrInfo.h
llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
llvm/lib/Target/M68k/M68kInstrInfo.cpp
llvm/lib/Target/M68k/M68kInstrInfo.h
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
llvm/lib/Target/MSP430/MSP430InstrInfo.h
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.h
llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/lib/Target/Mips/MipsSEInstrInfo.h
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
llvm/lib/Target/Sparc/SparcInstrInfo.cpp
llvm/lib/Target/Sparc/SparcInstrInfo.h
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/lib/Target/VE/VEInstrInfo.cpp
llvm/lib/Target/VE/VEInstrInfo.h
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
llvm/lib/Target/XCore/XCoreInstrInfo.cpp
llvm/lib/Target/XCore/XCoreInstrInfo.h
llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
llvm/lib/Target/Xtensa/XtensaInstrInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 882cadea223695..b8a3c2ac2ac83d 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1018,10 +1018,16 @@ class TargetInstrInfo : public MCInstrInfo {
/// The source and destination registers may overlap, which may require a
/// careful implementation when multiple copy instructions are required for
/// large registers. See for example the ARM target.
+ ///
+ /// If RenamableDest is true, the copy instruction's destination operand is
+ /// marked renamable.
+ /// If RenamableSrc is true, the copy instruction's source operand is
+ /// marked renamable.
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const DebugLoc &DL,
- MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const {
+ MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest = false,
+ bool RenamableSrc = false) const {
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
}
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index c2b8c39662bb64..38bd0b0ba4114c 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -823,7 +823,9 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
}
copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
- SrcMO.getReg(), SrcMO.isKill());
+ SrcMO.getReg(), SrcMO.isKill(),
+ DstMO.getReg().isPhysical() ? DstMO.isRenamable() : false,
+ SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);
if (MI->getNumOperands() > 2)
transferImplicitOperands(MI, TRI);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 2d41aff605a54e..9fab8867432410 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -4851,7 +4851,9 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
if (AArch64::GPR32spRegClass.contains(DestReg) &&
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
const TargetRegisterInfo *TRI = &getRegisterInfo();
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 1580cdc0a2ba24..dbd820afb3be06 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -344,7 +344,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
llvm::ArrayRef<unsigned> Indices) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index ff444543392687..d826ae8c5da23a 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -40,7 +40,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
unsigned VectorComponents = 0;
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
index f720e4656348c8..c767ecb24590b3 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
@@ -73,7 +73,8 @@ class R600InstrInfo final : public R600GenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 84d25a1fbd2722..a857bdba53c3e8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -794,7 +794,8 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
unsigned Size = RI.getRegSizeInBits(*RC);
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index badfd91c0b9727..4fd9b4366159be 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -255,7 +255,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void materializeImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const DebugLoc &DL,
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 9b5e45cb5fe974..78db68fca3050a 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -281,7 +281,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
assert(ARC::GPR32RegClass.contains(SrcReg) &&
"Only GPR32 src copy supported.");
assert(ARC::GPR32RegClass.contains(DestReg) &&
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h
index 1875aafbde8261..e25f9902522607 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.h
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.h
@@ -65,7 +65,8 @@ class ARCInstrInfo : public ARCGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 1199052ca97e9c..49513fe10945a0 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -892,7 +892,9 @@ void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
bool GPRDest = ARM::GPRRegClass.contains(DestReg);
bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 8521e3ef91399a..9e4e12a9a7441b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -209,7 +209,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
index 396328e958d18a..a38aa3de40d901 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
@@ -42,7 +42,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// Need to check the arch.
MachineFunction &MF = *MBB.getParent();
const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.h b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
index 984bec4e64490b..84241fb8a9a66b 100644
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.h
@@ -39,7 +39,8 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIndex,
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 09bcd3109f2b30..d1e07b6703a5e6 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -151,7 +151,8 @@ Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// Handle SPR, DPR, and QPR copies.
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.h b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
index 8915da8c5bf3c8..70ee3270e64ac9 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.h
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.h
@@ -39,7 +39,8 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
index 18b7365fc5aa0f..7b0f8d74e77c2f 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp
@@ -42,7 +42,8 @@ AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
unsigned Opc;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h
index 28c0e0319d46ed..8eb4292f2422d2 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.h
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.h
@@ -75,7 +75,8 @@ class AVRInstrInfo : public AVRGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex,
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.cpp b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
index 2209f1f1462b43..1b07e7ffc0d313 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.cpp
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.cpp
@@ -31,7 +31,8 @@ BPFInstrInfo::BPFInstrInfo()
void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
if (BPF::GPRRegClass.contains(DestReg, SrcReg))
BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.h b/llvm/lib/Target/BPF/BPFInstrInfo.h
index 354aca1bd2f93b..a6b6fd7dc4d96f 100644
--- a/llvm/lib/Target/BPF/BPFInstrInfo.h
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.h
@@ -31,7 +31,8 @@ class BPFInstrInfo : public BPFGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
index 6baca84ab3d0a6..a2bb87bcaaf942 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
@@ -478,7 +478,8 @@ void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
if (CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::CARRYRegClass.contains(DestReg)) {
if (STI.hasE2()) {
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
index 4e3866b1188ca0..54c1106310d856 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
@@ -55,7 +55,8 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 3f6de365fe393e..7c77bf2b31b8e4 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -857,7 +857,9 @@ static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
unsigned KillFlag = getKillRegState(KillSrc);
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 4efc62fd717c65..854c3694ceba76 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -174,7 +174,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// large registers. See for example the ARM target.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
/// Store the specified register of the given register class to the specified
/// stack frame index. The store instruction is to be added to the given
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index 9f3d9b7aaa6f9c..06ef5d114f4556 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -35,8 +35,8 @@ void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Position,
const DebugLoc &DL,
MCRegister DestinationRegister,
- MCRegister SourceRegister,
- bool KillSource) const {
+ MCRegister SourceRegister, bool KillSource,
+ bool RenamableDest, bool RenamableSrc) const {
if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
llvm_unreachable("Impossible reg-to-reg copy");
}
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
index 8ad2b9237c9284..2630464f0a76f8 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h
@@ -49,7 +49,9 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
const DebugLoc &DL, MCRegister DestinationRegister,
- MCRegister SourceRegister, bool KillSource) const override;
+ MCRegister SourceRegister, bool KillSource,
+ bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Position,
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
index 90d94e96b0efdd..9059da460f1358 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
@@ -39,7 +39,9 @@ MCInst LoongArchInstrInfo::getNop() const {
void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc))
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
index d66b2cb8efb337..ef9970783107ea 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
@@ -31,7 +31,8 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
index 338db45782c961..23c5c76a47479b 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -663,7 +663,8 @@ bool M68kInstrInfo::isPCRelRegisterOperandLegal(
void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DstReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
unsigned Opc = 0;
// First deal with the normal symmetric copies.
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h
index d1e1e1cd99987b..5d81956d89fdf6 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.h
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.h
@@ -271,7 +271,8 @@ class M68kInstrInfo : public M68kGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
unsigned &Size, unsigned &Offset,
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
index 74057165166439..ae1228ceaa4e33 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -90,7 +90,8 @@ void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
unsigned Opc;
if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
Opc = MSP430::MOV16rr;
diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
index b8d015a21cd150..113a22318bec52 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h
+++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h
@@ -37,7 +37,8 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index 30ac96936de287..1bc1ed7ab93e31 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -69,7 +69,8 @@ Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
unsigned Opc = 0;
if (Mips::CPU16RegsRegClass.contains(DestReg) &&
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.h b/llvm/lib/Target/Mips/Mips16InstrInfo.h
index e8567ee3b9ce5c..8e73c8079b0f8f 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.h
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.h
@@ -50,7 +50,8 @@ class Mips16InstrInfo : public MipsInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index b99ddfab2a47d6..87e9ef1c26420a 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -83,7 +83,8 @@ Register MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
unsigned Opc = 0, ZeroReg = 0;
bool isMicroMips = Subtarget.inMicroMipsMode();
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.h b/llvm/lib/Target/Mips/MipsSEInstrInfo.h
index a8855e26ad10f6..36bddba10410ce 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.h
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.h
@@ -44,7 +44,8 @@ class MipsSEInstrInfo : public MipsInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index 673858f92e7cee..bec40874c89488 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -32,7 +32,8 @@ NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {}
void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
index d6cbeae6984c9f..f674a00bc351bf 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
@@ -53,7 +53,8 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
// Branch analysis.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 81f16eb1a905b0..48833e8f88066c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1678,7 +1678,8 @@ static unsigned getCRBitValue(unsigned CRBit) {
void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// We can end up with self copies and similar things as a result of VSX copy
// legalization. Promote them here.
const TargetRegisterInfo *TRI = &getRegisterInfo();
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 1e2687f92c61e5..40996f6fbb75e1 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -454,7 +454,8 @@ class PPCInstrInfo : public PPCGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9dd79027d7a162..77072edab4d138 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -440,12 +440,14 @@ void RISCVInstrInfo::copyPhysRegVector(
void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(SrcReg,
+ getKillRegState(KillSrc) | getRenamableRegState(RenamableSrc))
.addImm(0);
return;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index ecb7982b3e5e36..f25e5ee42a7373 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -84,7 +84,8 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
const TargetRegisterClass *RegClass) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index dac7640cdddd69..e8a6b4fdbae977 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -241,7 +241,8 @@ unsigned SPIRVInstrInfo::insertBranch(
void SPIRVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// Actually we don't need this COPY instruction. However if we do nothing with
// it, post RA pseudo instrs expansion just removes it and we get the code
// with undef registers. Therefore, we need to replace all uses of dst with
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
index 95f3874913572c..67d2d979cb5a15 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
@@ -51,7 +51,8 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
int *BytesAdded = nullptr) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
bool expandPostRAPseudo(MachineInstr &MI) const override;
};
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 2727a9f2efbb1e..0bb2540a97d728 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -438,7 +438,8 @@ bool SparcInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
unsigned numSubRegs = 0;
unsigned movOpc = 0;
const unsigned *subRegIdx = nullptr;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h
index a7bb34c6c8e77a..fc04542c819d46 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.h
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h
@@ -87,7 +87,8 @@ class SparcInstrInfo : public SparcGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index d0758891fe570a..91db858f5cdaf6 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -857,7 +857,9 @@ bool SystemZInstrInfo::PredicateInstruction(
void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
// Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
// super register in case one of the subregs is undefined.
// This handles ADDR128 too.
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 61338b0816155a..cc8a4ccd234cd1 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -276,7 +276,8 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
ArrayRef<MachineOperand> Pred) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIndex,
diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp
index c001dc4d92b9af..fccbed3bdec8ba 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.cpp
+++ b/llvm/lib/Target/VE/VEInstrInfo.cpp
@@ -359,7 +359,8 @@ static void copyPhysSubRegs(MachineBasicBlock &MBB,
void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, const DebugLoc &DL,
MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const {
+ bool KillSrc, bool RenamableDest,
+ bool RenamableSrc) const {
if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) {
BuildMI(MBB, I, DL, get(VE::ORri), DestReg)
diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h
index 4fcc479a13d575..3a9718f2f26032 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.h
+++ b/llvm/lib/Target/VE/VEInstrInfo.h
@@ -81,7 +81,8 @@ class VEInstrInfo : public VEGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
/// Stack Spill & Reload {
Register isLoadFromStackSlot(const MachineInstr &MI,
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index 32a4accd040ebe..75011ab3c8721e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -57,7 +57,9 @@ bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest,
+ bool RenamableSrc) const {
// This method is called by post-RA expansion, which expects only pregs to
// exist. However we need to handle both here.
auto &MRI = MBB.getParent()->getRegInfo();
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
index c1e1a790c60e2c..8cb692f9bc0c47 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
@@ -47,7 +47,8 @@ class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
unsigned OpIdx1,
unsigned OpIdx2) const override;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 39ba7ea777909c..30428b9c3dcddb 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4293,7 +4293,8 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// First deal with the normal symmetric copies.
bool HasAVX = Subtarget.hasAVX();
bool HasVLX = Subtarget.hasVLX();
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 3100a9e5699f0a..1c6362f911e4af 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -418,7 +418,8 @@ class X86InstrInfo final : public X86GenInstrInfo {
Register FalseReg) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex,
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index ae2e0fec3f899f..90a195e928a590 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -331,7 +331,8 @@ XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const {
void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h
index 1dafb6ea7d2116..7f330539dd76af 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.h
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h
@@ -64,7 +64,8 @@ class XCoreInstrInfo : public XCoreGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
index 491defb8676437..2263aadcb0dd3f 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -105,7 +105,8 @@ void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc) const {
+ MCRegister SrcReg, bool KillSrc,
+ bool RenamableDest, bool RenamableSrc) const {
// The MOV instruction is not present in core ISA,
// so use OR instruction.
if (Xtensa::ARRegClass.contains(DestReg, SrcReg))
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
index 37f157f832464b..8bf3f0618f2857 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
@@ -49,7 +49,8 @@ class XtensaInstrInfo : public XtensaGenInstrInfo {
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
- bool KillSrc) const override;
+ bool KillSrc, bool RenamableDest = false,
+ bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
diff --git a/llvm/test/CodeGen/RISCV/renamable-copy.mir b/llvm/test/CodeGen/RISCV/renamable-copy.mir
new file mode 100644
index 00000000000000..06f17f4edbccfa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/renamable-copy.mir
@@ -0,0 +1,31 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=riscv32 -simplify-mir \
+# RUN: -run-pass=postrapseudos | FileCheck --check-prefix=RV32 %s
+# RUN: llc -o - %s -mtriple=riscv64 -simplify-mir \
+# RUN: -run-pass=postrapseudos | FileCheck --check-prefix=RV64 %s
+
+--- |
+ define void @foo() {
+ entry:
+ ret void
+ }
+...
+---
+name: foo
+body: |
+ bb.0.entry:
+ liveins: $x11
+ ; RV32-LABEL: name: foo
+ ; RV32: liveins: $x11
+ ; RV32-NEXT: {{ $}}
+ ; RV32-NEXT: $x10 = ADDI renamable $x11, 0
+ ; RV32-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV64-LABEL: name: foo
+ ; RV64: liveins: $x11
+ ; RV64-NEXT: {{ $}}
+ ; RV64-NEXT: $x10 = ADDI renamable $x11, 0
+ ; RV64-NEXT: PseudoRET implicit $x10
+ renamable $x10 = COPY renamable $x11
+ PseudoRET implicit $x10
+...
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