[llvm] [RISCV] Convert vmerge.vvm with same mask as true to vmv.v.v (PR #106108)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 26 10:23:47 PDT 2024
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/106108
This is a WIP patch that moves part of performCombineVMergeAndVOps to RISCVVectorPeephole by converting vmerge.vvm to vmv.v.v when it has the same mask as its true operand.
Posted as a draft to showcase the policy regressions that https://github.com/llvm/llvm-project/pull/105788 fixes
>From b11c15acbb5364edca431ab875ae8e36003b51e2 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Tue, 27 Aug 2024 01:20:57 +0800
Subject: [PATCH] WIP
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 42 +++----------------
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 18 +++++++-
.../fixed-vectors-strided-load-store-asm.ll | 7 +++-
.../RISCV/rvv/rvv-peephole-vmerge-vops.ll | 2 +-
4 files changed, 28 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 48fe788a81dffc..c4cd417986584f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3850,15 +3850,8 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
uint64_t TrueTSFlags = TrueMCID.TSFlags;
bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(TrueMCID);
- bool IsMasked = false;
const RISCV::RISCVMaskedPseudoInfo *Info =
RISCV::lookupMaskedIntrinsicByUnmasked(TrueOpc);
- if (!Info && HasTiedDest) {
- Info = RISCV::getMaskedPseudoInfo(TrueOpc);
- IsMasked = true;
- }
- assert(!(IsMasked && !HasTiedDest) && "Expected tied dest");
-
if (!Info)
return false;
@@ -3870,19 +3863,6 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
return false;
}
- // If True is masked then the vmerge must have either the same mask or an all
- // 1s mask, since we're going to keep the mask from True.
- if (IsMasked) {
- // FIXME: Support mask agnostic True instruction which would have an
- // undef passthru operand.
- SDValue TrueMask =
- getMaskSetter(True->getOperand(Info->MaskOpIdx),
- True->getOperand(True->getNumOperands() - 1));
- assert(TrueMask);
- if (!usesAllOnesMask(Mask, Glue) && getMaskSetter(Mask, Glue) != TrueMask)
- return false;
- }
-
// Skip if True has side effect.
if (TII->get(TrueOpc).hasUnmodeledSideEffects())
return false;
@@ -3948,24 +3928,13 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
return false;
}
- // If we end up changing the VL or mask of True, then we need to make sure it
- // doesn't raise any observable fp exceptions, since changing the active
- // elements will affect how fflags is set.
- if (TrueVL != VL || !IsMasked)
- if (mayRaiseFPException(True.getNode()) &&
- !True->getFlags().hasNoFPExcept())
- return false;
+ // Make sure it doesn't raise any observable fp exceptions, since changing the
+ // active elements will affect how fflags is set.
+ if (mayRaiseFPException(True.getNode()) && !True->getFlags().hasNoFPExcept())
+ return false;
SDLoc DL(N);
- // From the preconditions we checked above, we know the mask and thus glue
- // for the result node will be taken from True.
- if (IsMasked) {
- Mask = True->getOperand(Info->MaskOpIdx);
- Glue = True->getOperand(True->getNumOperands() - 1);
- assert(Glue.getValueType() == MVT::Glue);
- }
-
unsigned MaskedOpc = Info->MaskedPseudo;
#ifndef NDEBUG
const MCInstrDesc &MaskedMCID = TII->get(MaskedOpc);
@@ -3995,8 +3964,7 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
Ops.push_back(False);
const bool HasRoundingMode = RISCVII::hasRoundModeOp(TrueTSFlags);
- const unsigned NormalOpsEnd = TrueVLIndex - IsMasked - HasRoundingMode;
- assert(!IsMasked || NormalOpsEnd == Info->MaskOpIdx);
+ const unsigned NormalOpsEnd = TrueVLIndex - HasRoundingMode;
Ops.append(True->op_begin() + HasTiedDest, True->op_begin() + NormalOpsEnd);
Ops.push_back(Mask);
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 34e5d9224f7150..66492ff070423b 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -358,7 +358,23 @@ bool RISCVVectorPeephole::convertVMergeToVMv(MachineInstr &MI) const {
return false;
assert(MI.getOperand(4).isReg() && MI.getOperand(4).getReg() == RISCV::V0);
- if (!isAllOnesMask(V0Defs.lookup(&MI)))
+ auto TrueHasSameMask = [&]() {
+ MachineInstr *True = MRI->getVRegDef(MI.getOperand(3).getReg());
+ if (!True)
+ return false;
+ const RISCV::RISCVMaskedPseudoInfo *Info =
+ RISCV::getMaskedPseudoInfo(True->getOpcode());
+ if (!Info)
+ return false;
+ if (True->getOperand(1).getReg() != RISCV::NoRegister &&
+ TRI->lookThruCopyLike(True->getOperand(1).getReg(), MRI) !=
+ TRI->lookThruCopyLike(FalseReg, MRI))
+ return false;
+ return V0Defs.lookup(True)->getOperand(1).getReg() ==
+ V0Defs.lookup(&MI)->getOperand(1).getReg();
+ };
+
+ if (!isAllOnesMask(V0Defs.lookup(&MI)) && !TrueHasSameMask())
return false;
MI.setDesc(TII->get(NewOpc));
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
index e57b6a22dd6eab..5060a09c146cdc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
@@ -63,8 +63,9 @@ define void @gather_masked(ptr noalias nocapture %A, ptr noalias nocapture reado
; CHECK-NEXT: .LBB1_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a3, e8, m1, tu, mu
; CHECK-NEXT: vlse8.v v9, (a1), a4, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vadd.vv v9, v10, v9
; CHECK-NEXT: vse8.v v9, (a0)
@@ -344,10 +345,12 @@ define void @scatter_masked(ptr noalias nocapture %A, ptr noalias nocapture read
; CHECK-NEXT: li a4, 5
; CHECK-NEXT: .LBB7_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v9, (a1)
; CHECK-NEXT: vmv1r.v v10, v8
+; CHECK-NEXT: vsetvli zero, zero, e8, m1, tu, mu
; CHECK-NEXT: vlse8.v v10, (a0), a4, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vadd.vv v9, v10, v9
; CHECK-NEXT: vsse8.v v9, (a0), a4, v0.t
; CHECK-NEXT: addi a1, a1, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
index 6700920cebff0a..b637ca5361d977 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
@@ -1181,7 +1181,7 @@ define <vscale x 2 x i32> @true_tied_dest_vmerge_implicit_passthru(<vscale x 2 x
define <vscale x 2 x i32> @true_mask_vmerge_implicit_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl) {
; CHECK-LABEL: true_mask_vmerge_implicit_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl, i64 0)
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