[llvm] [AMDGPU][CodeGen][test] update mir test file with latest update_mir_test_check script (PR #106073)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 26 07:31:41 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-amdgpu
Author: Brox Chen (broxigarchen)
<details>
<summary>Changes</summary>
Run a scan with latest update_mir_test_checks.py and update impacted test files
This is to clean up the mir test files diff generated by python script version update
---
Patch is 932.09 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/106073.diff
159 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir (+91)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir (-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir (+30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir (+14-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir (+14-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir (+6-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir (+6-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir (+22-22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir (+149-116)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir (+48-36)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir (+20-34)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir (+20-34)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir (+20-34)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir (+20-34)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir (+90-72)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir (+80-68)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir (+33)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir (+16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir (+19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir (+24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir (+63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir (+30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir (+8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir (+8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop1.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sextload-local.mir (+8-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir (+30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir (+18-14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir (+10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir (+20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir (+12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir (+51)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir (+12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir (+20-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir (+12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zextload-local.mir (+8-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir (+14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir (+7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir (+11-11)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir (+16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir (+20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir (+72)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir (+12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir (+10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir (+22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir (+30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir (+7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir (+23)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir (+23)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir (+20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir (+27)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir (+19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir (+20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir (+20)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir (+27)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir (+22)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir (+17)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir (+6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir (+19)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir (+16)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir (-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-smed3.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-umed3.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir (+35-28)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir (+50-40)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir (+80-80)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.mir (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir (+168-38)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir (+12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir (+14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir (+1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir (+12-28)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir (+18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir (+34)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir (+5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir (+48)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir (+5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir (+5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir (+4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uniform-load-noclobber.mir (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir (+5)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir (+38)
- (modified) llvm/test/CodeGen/AMDGPU/artificial-terminators.mir (-4)
- (modified) llvm/test/CodeGen/AMDGPU/i1_copy_phi_with_phi_incoming_value.mir (-7)
- (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir (-48)
- (modified) llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness-wave32.mir (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/release-vgprs.mir (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir (+1-1)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
index 789385dcbae829..c2fe96f9324dff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
@@ -24,6 +24,7 @@ body: |
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX9-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-CONTRACT-LABEL: name: test_f32_add_mul
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-CONTRACT-NEXT: {{ $}}
@@ -33,6 +34,7 @@ body: |
; GFX9-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; GFX9-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
; GFX9-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-DENORM-LABEL: name: test_f32_add_mul
; GFX9-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-DENORM-NEXT: {{ $}}
@@ -43,6 +45,7 @@ body: |
; GFX9-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX9-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-UNSAFE-LABEL: name: test_f32_add_mul
; GFX9-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-UNSAFE-NEXT: {{ $}}
@@ -52,6 +55,7 @@ body: |
; GFX9-UNSAFE-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[FMA]](s32)
; GFX9-UNSAFE-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-LABEL: name: test_f32_add_mul
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -62,6 +66,7 @@ body: |
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX10-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-CONTRACT-LABEL: name: test_f32_add_mul
; GFX10-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-CONTRACT-NEXT: {{ $}}
@@ -71,6 +76,7 @@ body: |
; GFX10-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; GFX10-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
; GFX10-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-DENORM-LABEL: name: test_f32_add_mul
; GFX10-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-DENORM-NEXT: {{ $}}
@@ -81,6 +87,7 @@ body: |
; GFX10-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[COPY2]]
; GFX10-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX10-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-UNSAFE-LABEL: name: test_f32_add_mul
; GFX10-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-UNSAFE-NEXT: {{ $}}
@@ -115,6 +122,7 @@ body: |
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY2]], [[FMUL]]
; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX9-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-CONTRACT-LABEL: name: test_f32_add_mul_rhs
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-CONTRACT-NEXT: {{ $}}
@@ -124,6 +132,7 @@ body: |
; GFX9-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; GFX9-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
; GFX9-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-DENORM-LABEL: name: test_f32_add_mul_rhs
; GFX9-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-DENORM-NEXT: {{ $}}
@@ -134,6 +143,7 @@ body: |
; GFX9-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY2]], [[FMUL]]
; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX9-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-UNSAFE-LABEL: name: test_f32_add_mul_rhs
; GFX9-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-UNSAFE-NEXT: {{ $}}
@@ -143,6 +153,7 @@ body: |
; GFX9-UNSAFE-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[FMA]](s32)
; GFX9-UNSAFE-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-LABEL: name: test_f32_add_mul_rhs
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -153,6 +164,7 @@ body: |
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY2]], [[FMUL]]
; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX10-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-CONTRACT-LABEL: name: test_f32_add_mul_rhs
; GFX10-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-CONTRACT-NEXT: {{ $}}
@@ -162,6 +174,7 @@ body: |
; GFX10-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; GFX10-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
; GFX10-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-DENORM-LABEL: name: test_f32_add_mul_rhs
; GFX10-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-DENORM-NEXT: {{ $}}
@@ -172,6 +185,7 @@ body: |
; GFX10-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY2]], [[FMUL]]
; GFX10-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
; GFX10-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-UNSAFE-LABEL: name: test_f32_add_mul_rhs
; GFX10-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-UNSAFE-NEXT: {{ $}}
@@ -209,6 +223,7 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV1]]
; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX9-CONTRACT-LABEL: name: test_add_mul_multiple_defs_z
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-CONTRACT-NEXT: {{ $}}
@@ -221,6 +236,7 @@ body: |
; GFX9-CONTRACT-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[UV1]]
; GFX9-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
+ ;
; GFX9-DENORM-LABEL: name: test_add_mul_multiple_defs_z
; GFX9-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-DENORM-NEXT: {{ $}}
@@ -234,6 +250,7 @@ body: |
; GFX9-DENORM-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV1]]
; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX9-UNSAFE-LABEL: name: test_add_mul_multiple_defs_z
; GFX9-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-UNSAFE-NEXT: {{ $}}
@@ -246,6 +263,7 @@ body: |
; GFX9-UNSAFE-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-UNSAFE-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[UV1]]
; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[FMA]](s32)
+ ;
; GFX10-LABEL: name: test_add_mul_multiple_defs_z
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-NEXT: {{ $}}
@@ -259,6 +277,7 @@ body: |
; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV1]]
; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX10-CONTRACT-LABEL: name: test_add_mul_multiple_defs_z
; GFX10-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-CONTRACT-NEXT: {{ $}}
@@ -271,6 +290,7 @@ body: |
; GFX10-CONTRACT-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX10-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[UV1]]
; GFX10-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
+ ;
; GFX10-DENORM-LABEL: name: test_add_mul_multiple_defs_z
; GFX10-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-DENORM-NEXT: {{ $}}
@@ -284,6 +304,7 @@ body: |
; GFX10-DENORM-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX10-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FMUL]], [[UV1]]
; GFX10-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX10-UNSAFE-LABEL: name: test_add_mul_multiple_defs_z
; GFX10-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-UNSAFE-NEXT: {{ $}}
@@ -328,6 +349,7 @@ body: |
; GFX9-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[FMUL]]
; GFX9-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX9-CONTRACT-LABEL: name: test_add_mul_rhs_multiple_defs_z
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-CONTRACT-NEXT: {{ $}}
@@ -340,6 +362,7 @@ body: |
; GFX9-CONTRACT-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[UV1]]
; GFX9-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
+ ;
; GFX9-DENORM-LABEL: name: test_add_mul_rhs_multiple_defs_z
; GFX9-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-DENORM-NEXT: {{ $}}
@@ -353,6 +376,7 @@ body: |
; GFX9-DENORM-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[FMUL]]
; GFX9-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX9-UNSAFE-LABEL: name: test_add_mul_rhs_multiple_defs_z
; GFX9-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX9-UNSAFE-NEXT: {{ $}}
@@ -365,6 +389,7 @@ body: |
; GFX9-UNSAFE-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX9-UNSAFE-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[UV1]]
; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[FMA]](s32)
+ ;
; GFX10-LABEL: name: test_add_mul_rhs_multiple_defs_z
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-NEXT: {{ $}}
@@ -378,6 +403,7 @@ body: |
; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX10-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[FMUL]]
; GFX10-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX10-CONTRACT-LABEL: name: test_add_mul_rhs_multiple_defs_z
; GFX10-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-CONTRACT-NEXT: {{ $}}
@@ -390,6 +416,7 @@ body: |
; GFX10-CONTRACT-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX10-CONTRACT-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[UV1]]
; GFX10-CONTRACT-NEXT: $vgpr0 = COPY [[FMA]](s32)
+ ;
; GFX10-DENORM-LABEL: name: test_add_mul_rhs_multiple_defs_z
; GFX10-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-DENORM-NEXT: {{ $}}
@@ -403,6 +430,7 @@ body: |
; GFX10-DENORM-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)
; GFX10-DENORM-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[UV1]], [[FMUL]]
; GFX10-DENORM-NEXT: $vgpr0 = COPY [[FADD]](s32)
+ ;
; GFX10-UNSAFE-LABEL: name: test_add_mul_rhs_multiple_defs_z
; GFX10-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; GFX10-UNSAFE-NEXT: {{ $}}
@@ -448,6 +476,7 @@ body: |
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-CONTRACT-LABEL: name: test_half_add_mul
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-CONTRACT-NEXT: {{ $}}
@@ -461,6 +490,7 @@ body: |
; GFX9-CONTRACT-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMA]](s16)
; GFX9-CONTRACT-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-DENORM-LABEL: name: test_half_add_mul
; GFX9-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-DENORM-NEXT: {{ $}}
@@ -475,6 +505,7 @@ body: |
; GFX9-DENORM-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX9-DENORM-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-UNSAFE-LABEL: name: test_half_add_mul
; GFX9-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-UNSAFE-NEXT: {{ $}}
@@ -488,6 +519,7 @@ body: |
; GFX9-UNSAFE-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMA]](s16)
; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-UNSAFE-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-LABEL: name: test_half_add_mul
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -502,6 +534,7 @@ body: |
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX10-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-CONTRACT-LABEL: name: test_half_add_mul
; GFX10-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-CONTRACT-NEXT: {{ $}}
@@ -515,6 +548,7 @@ body: |
; GFX10-CONTRACT-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMA]](s16)
; GFX10-CONTRACT-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX10-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-DENORM-LABEL: name: test_half_add_mul
; GFX10-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-DENORM-NEXT: {{ $}}
@@ -529,6 +563,7 @@ body: |
; GFX10-DENORM-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX10-DENORM-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX10-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-UNSAFE-LABEL: name: test_half_add_mul
; GFX10-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-UNSAFE-NEXT: {{ $}}
@@ -575,6 +610,7 @@ body: |
; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX9-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-CONTRACT-LABEL: name: test_half_add_mul_rhs
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-CONTRACT-NEXT: {{ $}}
@@ -588,6 +624,7 @@ body: |
; GFX9-CONTRACT-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMA]](s16)
; GFX9-CONTRACT-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-DENORM-LABEL: name: test_half_add_mul_rhs
; GFX9-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-DENORM-NEXT: {{ $}}
@@ -602,6 +639,7 @@ body: |
; GFX9-DENORM-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX9-DENORM-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX9-UNSAFE-LABEL: name: test_half_add_mul_rhs
; GFX9-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9-UNSAFE-NEXT: {{ $}}
@@ -615,6 +653,7 @@ body: |
; GFX9-UNSAFE-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMA]](s16)
; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-UNSAFE-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-LABEL: name: test_half_add_mul_rhs
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-NEXT: {{ $}}
@@ -629,6 +668,7 @@ body: |
; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX10-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX10-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-CONTRACT-LABEL: name: test_half_add_mul_rhs
; GFX10-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-CONTRACT-NEXT: {{ $}}
@@ -642,6 +682,7 @@ body: |
; GFX10-CONTRACT-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMA]](s16)
; GFX10-CONTRACT-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX10-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-DENORM-LABEL: name: test_half_add_mul_rhs
; GFX10-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-DENORM-NEXT: {{ $}}
@@ -656,6 +697,7 @@ body: |
; GFX10-DENORM-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD]](s16)
; GFX10-DENORM-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX10-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+ ;
; GFX10-UNSAFE-LABEL: name: test_half_add_mul_rhs
; GFX10-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10-UNSAFE-NEXT: {{ $}}
@@ -706,6 +748,7 @@ body: |
; GFX9-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX9-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX9-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX9-CONTRACT-LABEL: name: test_double_add_mul
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX9-CONTRACT-NEXT: {{ $}}
@@ -723,6 +766,7 @@ body: |
; GFX9-CONTRACT-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX9-CONTRACT-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX9-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX9-DENORM-LABEL: name: test_double_add_mul
; GFX9-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX9-DENORM-NEXT: {{ $}}
@@ -741,6 +785,7 @@ body: |
; GFX9-DENORM-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX9-DENORM-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX9-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX9-UNSAFE-LABEL: name: test_double_add_mul
; GFX9-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX9-UNSAFE-NEXT: {{ $}}
@@ -758,6 +803,7 @@ body: |
; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX9-UNSAFE-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX9-UNSAFE-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX10-LABEL: name: test_double_add_mul
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX10-NEXT: {{ $}}
@@ -776,6 +822,7 @@ body: |
; GFX10-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX10-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX10-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX10-CONTRACT-LABEL: name: test_double_add_mul
; GFX10-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX10-CONTRACT-NEXT: {{ $}}
@@ -793,6 +840,7 @@ body: |
; GFX10-CONTRACT-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX10-CONTRACT-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX10-CONTRACT-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX10-DENORM-LABEL: name: test_double_add_mul
; GFX10-DENORM: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX10-DENORM-NEXT: {{ $}}
@@ -811,6 +859,7 @@ body: |
; GFX10-DENORM-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX10-DENORM-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX10-DENORM-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX10-UNSAFE-LABEL: name: test_double_add_mul
; GFX10-UNSAFE: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX10-UNSAFE-NEXT: {{ $}}
@@ -869,6 +918,7 @@ body: |
; GFX9-NEXT: $vgpr0 = COPY [[UV]](s32)
; GFX9-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GFX9-NEXT: S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr1
+ ;
; GFX9-CONTRACT-LABEL: name: test_double_add_mul_rhs
; GFX9-CONTRACT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
; GFX9-CONTRACT-NE...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/106073
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