[llvm] [TII][RISCV] Add renamable bit to copyPhysReg (PR #91179)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 26 05:25:06 PDT 2024
BeMg wrote:
Use the renamable bit on `RISCVInstrInfo::copyPhysReg` and add a mir testcase
https://github.com/llvm/llvm-project/pull/91179
More information about the llvm-commits
mailing list